C8051F575-IMR Silicon Labs, C8051F575-IMR Datasheet - Page 216

• Manufacturer Part Number: C8051F575-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB SPI UART I2C
• Manufacturer: Silicon Labs

Specifications of C8051F575-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F55x/56x/57x
22. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. A block diagram of the SMBus peripheral and
the associated SFRs is shown in Figure 22.1.
216
M
A
S
T
E
R
Interrupt
Request
M
O
T
X
D
E
SMB0CN
S
T
A
S
O
T
Q
A
C
K
R
R
O
A
B
L
S
T
A
C
K
S
I
IRQ Generation
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SMBUS CONTROL LOGIC
M
E
N
S
B
Figure 22.1. SMBus Block Diagram
N
H
I
SMB0CF
B
U
S
Y
O
E
X
T
H
D
L
M
O
S
B
T
E
M
S
B
E
F
T
M
S
B
C
S
1
7
M
C
S
B
S
0
6
Data Path
SMB0DAT
5
Control
4
3
Rev. 1.1
2
1
0
00
01
10
11
Control
SDA
Control
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
N
N
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O