74ALVCH16501DGG,11 NXP Semiconductors, 74ALVCH16501DGG,11 Datasheet
74ALVCH16501DGG,11
Specifications of 74ALVCH16501DGG,11
74ALVCH16501DG-T
935262543118
Related parts for 74ALVCH16501DGG,11
74ALVCH16501DGG,11 Summary of contents
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Rev. 03 — 2 April 2010 1. General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +85 °C 74ALVCH16501DGG −40 °C to +85 °C 74ALVCH16501DL 4. Functional diagram A10 16 A11 17 A12 19 A13 20 A14 21 A15 23 A16 24 A17 26 OEAB 1 LEAB 2 CPAB 55 Fig 1. Logic symbol 74ALVCH16501_3 Product data sheet ...
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... NXP Semiconductors Fig 3. Bus hold circuit OEAB OEBA Fig 4. Logic diagram 74ALVCH16501_3 Product data sheet V CC data input CPBA LEBA CPAB LEAB IDENTICAL CHANNELS All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 74ALVCH16501 18-bit universal bus transceiver; 3-state ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin OEAB 1 LEAB A17 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 GND 4, 11, 18, 25, 29, 32, 39, 46, 53 22, 35 OEBA 27 LEBA 28 74ALVCH16501_3 Product data sheet 74ALVCH16501 1 OEAB LEAB ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin CPBA B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 CPAB 55 6. Functional description 6.1 Function table [1] Table 3. Function table Inputs OEAB LEAB CPAB ↓ ↓ ↑ ↑ [1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA. ...
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... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I ground current GND T storage temperature stg P total power dissipation tot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter = −40 °C to +85 °C T amb f maximum frequency max t propagation delay pd t enable time en t disable time dis 74ALVCH16501_3 Product data sheet ...
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... NXP Semiconductors Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Symbol Parameter t pulse width W t set-up time su t hold time h C power dissipation PD capacitance [1] All typical values are measured at T [2] Typical values are measured at V [3] ...
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... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output levels that occur with the output load Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An) OEAB, OEBA input An, Bn output LOW-to-OFF OFF-to-LOW An, Bn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...
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... NXP Semiconductors Measurement points are given in V and V are typical output levels that occur with the output load Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width An, Bn input CPxx, LExx ...
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... NXP Semiconductors 12. Test information Test data is given in Table Definitions for test circuit Load resistance Load capacitance includes jig and probe capacitance Termination resistance should be equal External voltage for measuring switching times. EXT Fig 10. Load circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 13. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors SSOP56: plastic shrink small outline package; 56 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT371-1 Fig 12 ...
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... Release date Data sheet status 74ALVCH16501_3 20100402 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ALVCH16501_3 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 74ALVCH16501 18-bit universal bus transceiver; 3-state © ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Test information ...