TDA8035HN/C1,151 NXP Semiconductors, TDA8035HN/C1,151 Datasheet - Page 12

• Manufacturer Part Number: TDA8035HN/C1,151
• Description: Interface - Specialized SMART CARD INTERFACE
• Manufacturer: NXP Semiconductors

Specifications of TDA8035HN/C1,151

• Rohs: yes
• Factory Pack Quantity: 490

NXP Semiconductors
TDA8035HN
Product data sheet
COMPANY PUBLIC
8.5 CS control
8.6 Shutdown mode and Deep Shutdown mode
The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is
high, the system interface signals operate as described. When CS is low, the signals
CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN_5V/3VN and
AUX1UC and AUX2UC are set to high impedance pull-up mode and data is no longer
passed to or from the smart card. The OFFN output is a 3-state output.
After power-on reset, the circuit enters the Shutdown mode if CMDVCCN input pin is set
to a logic high. A minimum number of circuits are active while waiting for the
microcontroller to start a session.
A Deep Shutdown mode can be entered by forcing CMDVCCN input pin to a logic-High
state and EN_5V/3VN,
can only be entered when the smart card reader is inactive. In Deep Shutdown mode, all
circuits are disabled. The OFFN pin follows the status of PRESN pin. To exit Deep
Shutdown mode, change the state of one or more of the three control pins.
shows the control sequence for entering and exiting.
1. All card contacts are inactive (approximately 200  to GND).
2. I/OUC, AUX1UC and AUX2UC are high impedance (10 k pull-up resistor connected
3. Voltage generators are stopped.
4. Voltage supervisor is active.
5. The internal oscillator runs at its low frequency.
Fig 7.
to V
(internal pin)
EN_5V/3VN
CMDVCCN
EN_1.8VN
PRESN
DD(INTF)
OFFN
Mode
Shutdown mode and Deep Shutdown mode
V
CC
Shutdown
DEACTIVATION
).
SEQUENCE
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 3 December 2012
Activation
EN_1.8VN
Shutdown
input pins to a logic-Low state. Deep Shutdown mode
Deep Shutdown
EN_1.8VN
Shutdown
debounce
TDA8035HN
Smart card interface
are latched. I/OUC,
© NXP B.V. 2012. All rights reserved.
Figure 8
Activation
001aan751
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