74LVC16374ADG-T NXP Semiconductors, 74LVC16374ADG-T Datasheet
74LVC16374ADG-T
Specifications of 74LVC16374ADG-T
Related parts for 74LVC16374ADG-T
74LVC16374ADG-T Summary of contents
Page 1
D-type flip-flop tolerant; 3-state Rev. 11 — 16 January 2013 1. General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74LVC16374ADL 74LVCH16374ADL 40 C to +125 C 74LVC16374ADGG 74LVCH16374ADGG 40 C to +125 C 74LVC16374ABX 74LVCH16374ABX 4. Functional diagram 1 1OE 2OE 47 1D0 46 1D1 44 1D2 43 1D3 41 1D4 40 1D5 38 1D6 ...
Page 3
... NXP Semiconductors 1D0 1CP 1OE Fig 3. Logic diagram Fig 4. Bus hold circuit 74LVC_LVCH16374A Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 1Q0 2D0 FF1 2CP 2OE to 7 other channels V CC data input mna705 All information provided in this document is subject to legal disclaimers. ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 74LVC_LVCH16374A Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 74LVC16374A 74LVCH16374A 1CP 1OE 1D0 1Q0 3 46 1D1 1Q1 4 45 GND GND 5 44 ...
Page 5
... NXP Semiconductors terminal 1 index area (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVC_LVCH16374A Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 74LVC16374A ...
Page 6
... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1OE, 2OE 1, 24 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1Q0 to 1Q7 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 ...
Page 7
... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter P total power dissipation tot [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. ...
Page 8
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output = 100 voltage 4 mA 8 mA 12 mA 18 mA 24 mA ...
Page 9
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I bus hold V = 1.95 V BHHO CC HIGH overdrive V = 3.6 V current CC [1] All typical values are measured at V [2] The bus hold circuit is switched off when V [3] Valid for data inputs (74LVCH16374A) only ...
Page 10
... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t set-up time nDn to nCP; see hold time nDn to nCP; see maximum see Figure 7 ...
Page 11
... NXP Semiconductors 11. Waveforms nCP input nQn output Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 7. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency nCP input ...
Page 12
... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 9. 3-state enable and disable times Table 8. Measurement points ...
Page 13
... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 9 ...
Page 14
... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
Page 15
... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 16
... NXP Semiconductors HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 0.5 mm terminal 1 index area A10 terminal 1 index area D1 Dimensions Unit max 0.50 0.05 0.35 4.1 mm nom 0.48 0.02 0.30 4.0 min 0.46 0.00 0.25 3.9 Outline version ...
Page 17
... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVC_LVCH16374A v.11 20130116 • Modifications: • 74LVC_LVCH16374A v.10 20120301 74LVC_LVCH16374A v ...
Page 18
... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 19
... D-type flip-flop tolerant; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 20
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Abbreviations ...