DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 158

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has
cleared (falling edge detect of LORC)
Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has
cleared (falling edge detect of V52LNK).
Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has
cleared (falling edge detect of RDMA).
Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLK pin has not
transitioned for one channel time (rising edge detect of LORC).
Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal.
(G.965). This is the rising edge detect of V52LNK.
Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in
frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This
is the rising edge detect of RDMA.
LORCC
7
0
RLS3 (E1 Mode)
Receive Latched Status Register 3
092h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
6
0
V52LNKC
5
0
RDMAC
158 of 273
0
4
RLS3
for T1 mode.
LORCD
3
0
—
2
0
V52LNKD
1
0
RDMAD
0
0