DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 266

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

13.3
Table 13-2. ID Code Structure
DS26528
DS26524
13.4
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included with the DS26524 design. This test register is the identification register and
is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
13.4.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells,
and is n bits in length. See
13.4.2 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which
provides a short path between JTDI and JTDO.
13.4.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Table 13-3. Boundary Scan Control Bits
CELL#
DEVICE
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
JTAG ID Codes
Test Registers
rm_rfsync(1)
rm_rfsync(1)
tchblk_clk(1)
tchblk_clk(1)
rsync(1)
rsync(1)
tsync(1)
tsync(1)
NAME
rser(1)
tser(1)
tsig(1)
tsig(1)
tclk(1)
—
—
—
—
—
—
—
Consult factory
Consult factory
REVISION
ID[31:28]
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
Table 13-3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
TYPE
0000000000110111
0000000000111001
DEVICE CODE
for all the cell bit locations and definitions.
ID[27:12]
CONTROL
CELL
11
16
0
2
5
8
266 of 273
CELL#
MANUFACTURER’S CODE
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
00010100001
00010100001
al_rsigf_flos(2)
rchblk_clk(2)
rchblk_clk(2)
rm_rfsync(2)
rm_rfsync(2)
ID[11:1]
rlf_ltc(2)
rsync(2)
rsync(2)
NAME
rser(2)
rsig(2)
rsig(2)
tsig(2)
tsig(2)
—
—
—
—
—
—
—
observe_only
observe_only
observe_only
observe_only
observe_only
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
controlr
output3
TYPE
REQUIRED
ID[0]
1
1
CONTROL
CELL
19
22
25
27
29
31
34
37