DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 165

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Receive-Signaling All-Ones Event (RSA1).
Bit 2: Receive-Signaling All-Zeros Event (RSA0).
Bit 1: Receive CRC-4 Multiframe Event (RCMF).
Bit 0: Receive Align Frame Event (RAF).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
7
0
RIM2 (E1 Mode Only)
Receive Interrupt Mask Register 2
0A1h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
5
0
165 of 273
0
4
RSA1
3
0
RSA0
2
0
RCMF
1
0
RAF
0
0

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