DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 235

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
DS26524 Quad T1/E1/J1 Transceiver
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSYSCLK
CHANNEL 31
CHANNEL 32
CHANNEL 1
1
RSER
LSB
LSB MSB
2
RSYNC
RMSYNC
3
RSYNC
CHANNEL 1
CHANNEL 31
CHANNEL 32
C/A D/B
C/A D/B
A
B
A
B
RSIG
RCHCLK
4
RCHBLK
NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE.
NOTE 2: RSYNC IS IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-SIDE ELASTIC STORE.
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