DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 232

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: BERT Bit-Error-Detected Event (BBED).
Bit 5: BERT Bit Counter Overflow Event (BBCO).
Bit 4: BERT Error Counter Overflow Event (BECO).
Bit 3: BERT Receive All-Ones Condition (BRA1).
Bit 2: BERT Receive All-Zeros Condition (BRA0).
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS)
Bit 0: BERT in Synchronization Condition (BSYNC).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
7
0
BSIM
BERT Status Interrupt Mask Register
110Fh + (10h x n): where n = 0 to 3, for Ports 1 to 4
BBED
6
0
BBCO
5
0
232 of 273
BECO
4
0
BRA1
3
0
BRA0
2
0
BRLOS
1
0
BSYNC
0
0

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