DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 23

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

REFCLKIO
DIGIOEN
RESETB
JTCLK
NAME
JTRST
MCLK
JTMS
JTDO
INTB
JTDI
BTS
M13
PIN
J12
R9
D8
H4
B7
A7
K4
F5
L5
J4
impedance
I, Pullup
I, Pullup
I, Pullup
I, Pullup
O, High
TYPE
I/O
U
I
I
I
I
Interrupt Bar. This active-low, open-drain output is asserted when an unmasked
interrupt event is detected. INTB will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global level,
framer, LIU, and BERT level.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins.
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLK must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
Reset Bar. Active-low reset. This input forces the complete DS26524 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference
clock. This allows for multiple DS26524s to share the same reference for
generation of the backplane clock. Hence, in a system consisting of multiple
DS26524s, one can be a master and others a slave using the same reference
clock.
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
SYSTEM INTERFACE
23 of 273
Table
TEST
9-12.
FUNCTION
DS26524 Quad T1/E1/J1 Transceiver
DD
for normal operation.