DS3172 Maxim Integrated, DS3172 Datasheet - Page 188
![no-image](/images/no-image-200.jpg)
DS3172
Manufacturer Part Number
DS3172
Description
Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
Manufacturer
Maxim Integrated
Datasheet
1.DS3171.pdf
(234 pages)
Specifications of DS3172
Part # Aliases
90-31720-000
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 4 to 3: Framing Error Insert Control (FEIC[1:0]) – These two bits control the framing error event to be
inserted.
Bit 2: Framing Error Insertion Enable (FEI) – When 0, framing error insertion is disabled. When 1, framing error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.
00 = single bit error in one frame.
01 = word error in one frame.
10 = single bit error in four consecutive frames.
11 = word error in four consecutive frames.
Reserved
15
--
0
7
0
Reserved
14
--
0
6
0
E3G751.TEIR
E3 G.751 Transmit Error Insertion Register
(1,3,5,7)1Ah
Reserved
13
--
0
5
0
FEIC1
12
--
0
0
4
188
Reserved
FEIC0
11
0
3
0
Reserved
FEI
10
0
2
0
Reserved
TSEI
9
0
1
0
Reserved
MEIMS
8
0
0
0
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