DS3172 Maxim Integrated, DS3172 Datasheet - Page 25
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DS3172
Manufacturer Part Number
DS3172
Description
Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
Manufacturer
Maxim Integrated
Datasheet
1.DS3171.pdf
(234 pages)
Specifications of DS3172
Part # Aliases
90-31720-000
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8 PIN DESCRIPTIONS
Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for
isolation of interconnect failures.
8.1 Short Pin Descriptions
Table 8-1. DS3174 Short Pin Descriptions
n=1,2,3,4 (port number); Ipu (input with pullup), Oz (output tri-stateable), (needs an external pullup or pulldown resistor to keep from floating),
Oa (Analog output), Ia (Analog input), IO (Bidirectional inout); all unused input pins without pullup should be tied low.
TLCLKn
TPOSn / TDATn
TNEGn
TXPn
TXNn
RLCLKn
RXPn
RXNn
RPOSn / RDATn
RNEGn / RLCVn
TOHn
TOHENn
TOHCLKn
TOHSOFn
ROHn
ROHCLKn
ROHSOFn
TCLKIn
TSOFIn
TSERn
TCLKOn / TGCLKn
TSOFOn / TDENn
RSERn
RCLKOn / RGCLKn
RSOFOn / RDENn
NAME
TYPE
Oa
Oa
Ia
Ia
Ia
Ia
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
Transmit Line Clock Output
Transmit Positive AMI / Data
Transmit Negative AMI
Transmit Positive analog
Transmit Negative analog
Receive Clock Input
Receive Positive analog
Receive Negative analog
Transmit Overhead
Transmit Overhead Enable
Transmit Overhead Clock
Transmit Overhead Start Of Frame
Receive Overhead
Receive Overhead Clock
Receive Overhead Start Of Frame
Transmit Line Clock Input
Transmit Start Of Frame Input
Transmit Serial Data
Transmit Clock Output / Gapped Clock
Transmit Framer Start Of Frame / Data Enable
Receive Serial Data
Receive / Clock Output / Gapped Clock
Receive Framer Start Of Frame / Data Enable
Positive AMI / Data
Negative AMI / Line Code Violation
DS3/E3 Overhead Interface
DS3/E3 Serial Data
FUNCTION
Line IO
25
PORT
V11
V14
W14
W6
Y6
Y12
W5
Y5
W15
Y15
U11
T14
T11
T12
T10
T13
U14
Y14
U12
V13
Y13
V12
W11
Y11
W12
4
C11
C14
B14
B6
A6
A12
B5
A5
B15
A15
D11
E14
E11
E12
E10
E13
D14
A14
D12
C13
A13
C12
B11
A11
B12
PORT
3
PIN #
PORT
Y8
V4
U4
M2
M1
W8
R2
R1
Y3
W3
U8
T5
V8
V7
U10
U5
Y2
W4
W7
T6
U7
Y7
T9
U9
T8
2
A8
C4
D4
J2
J1
B8
F2
F1
A3
B3
D8
E5
C8
C7
D10
D5
B2
B4
B7
E6
D7
A7
E9
D9
E8
PORT
1
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