XRT83L34ES Exar, XRT83L34ES Datasheet

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... T X FILT ER LINE & PULSE DRIVER SHAPER TRING_n LBO[3:0] TXON_n LOCAL ANALOG LOOPBACK PEAK RTIP_n RX DET ECTO R EQ UALIZER RRING_n & SLICER EQUALIZER CO NT ROL ICT TEST µ µ D[7:0] µ A[7:0] RESET • • FAX (510) 668-7017 www.exar.com REV. 1.0.1 PTS1 PTS2 PCLK ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE LOCK IAGRAM OF THE MCLKE1 MCLKT1 MASTER CLOCK SYNT HESIZER CLKSEL[2:0] One of four Channels, CHANNEL_n - (n TPOS_n/TDATA_n QRSS ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR • Error and Bipolar Violation Insertion and Detection • Receiver Line Attenuation Indication Output in 1dB steps • Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation • Transmit All Ones ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 XRT83L34 IGURE THE 103 TCLK_2 104 _2/TD ATA_2 105 TNE G _2/CO DE S_2 106 uP TS ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR GENERAL DESCRIPTION....................................................................................................1 A ................................................................................................................................................ 1 PPLICATIONS Figure 1. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ........................................... 1 Figure 2. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE ECEIVE ERMINATIONS Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .............. 37 Figure 15. Simplified Diagram for ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 18: M ABLE ICROPROCESSOR T 19: M ABLE ICROPROCESSOR ICROPROCESSOR EGISTER T 20: M ABLE ICROPROCESSOR T 21: M ABLE ICROPROCESSOR T 22: M ABLE ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 PIN DESCRIPTION BY FUNCTION RECEIVE SECTIONS IGNAL AME IN YPE RLOS_0 4 O RLOS_1 28 RLOS_2 75 RLOS_3 99 RCLK_0 5 O ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE RPOS_0 RDATA_0 RPOS_1/ 25 RDATA_1 RPOS_2/ 78 RDATA_2 RPOS_3/ 96 RDATA_3 RTIP_0 9 I RTIP_1 23 RTIP_2 80 ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE RXMUTE 73 RDY_DTACK Receive Muting upon LOS Command Input/READY or DTACK Output: The exact function ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE RXRES0 RXRES1 108 I 109 RCLKE 106 I µPTS1 D ESCRIPTION Receive External Resistor Control Pins - Hardware mode Receive ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TRANSMITTER SECTIONS IGNAL AME IN YPE TCLKE 107 I µPTS2 TTIP_0 13 O TTIP_1 TTIP_2 19 TTIP_3 84 90 TRING_0 15 O ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE TPOS_0 TDATA_0 TPOS_1/ 127 TDATA_1 TPOS_2/ 104 TDATA_2 TPOS_3/ 101 TDATA_3 D ESCRIPTION Transmit Positive-Polarity Data Input pin/Transmit ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE TNEG_0 CODES_0 TNEG_1/ 126 CODES_1 TNEG_2/ 105 CODES_2 TNEG_3/ 100 CODES_3 D ESCRIPTION Transmitter Negative-Polarity Data ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE TCLK_0 1 I TCLK_1 128 TCLK_2 103 TCLK_3 102 TAOS_0 69 I TAOS_1 70 TAOS_2 71 TAOS_3 72 WR_R/W 69 ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 MICROPROCESSOR INTERFACE IGNAL AME IN YPE HW_HOST 68 I WR_R TAOS_0 69 D ESCRIPTION HOST/HARDWARE Mode Control Input pin: This ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE RD_DS 70 TAOS_1 70 I Read Strobe/Data Strobe/Transmit All Ones Command Input - Channel 1: The exact function of this ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE ALE_AS 71 I TAOS_2 TAOS_3 72 D ESCRIPTION Address Latch Enable/Address Strobe/Transmit All Ones ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE RDY_DTACK 73 O RXMUTE ESCRIPTION Ready or DTACK Output/Receive Muting upon LOS Command Input pin: The exact ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE µPTS1 106 µPTS2 107 RCLKE 106 TCLKE 107 D[7] 42 I/O D[6] 43 D[5] 44 D[4] 45 D[3] ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE A[ A[5] 58 A[4] 59 A[3] 60 A[2] 61 A[1] 62 A[0] 63 JASEL1 57 JASEL0 58 EQC4 ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 JITTER ATTENUATOR IGNAL AME IN YPE JASEL0 58 I JASEL1 57 A[ ESCRIPTION Jitter Attenuator Select Pins - ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CLOCK SYNTHESIZER IGNAL AME IN YPE MCLKE1 32 I CLKSEL0 37 I CLKSEL1 38 CLKSEL2 39 D ESCRIPTION E1 Master Clock Input A 2.048MHz ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE MCLKT1 33 MCLKOUT 36 O ALARM FUNCTION//REDUNDANCY SUPPORT IGNAL AME IN YPE GAUGE ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE TRATIO 119 INT O RESET 121 SR/DR 16 LOOP1_0 42 I/O LOOP0_0 43 LOOP1_1 44 LOOP0_1 45 LOOP1_2 46 LOOP0_2 ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME IN YPE EQC4 59 I EQC3 60 EQC2 61 EQC1 62 EQC0 63 A[4] 59 A[3] 60 A[2] 61 A[1] ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME IN YPE TERSEL0 113 TERSEL1 112 ICT 120 I Termination Impedance Select pin 0 Termination Impedance Select pin 1 In the Hardware ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 POWER AND GROUND IGNAL AME IN YPE TGND_0 12 **** TGND_1 20 TGND_2 83 TGND_3 91 TVDD_0 14 **** TVDD_1 18 TVDD_2 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FUNCTIONAL DESCRIPTION The XRT83L34 is a fully integrated four-channel long-haul and short-haul transceiver intended for T1 systems. Simplified block diagrams of the device are shown in ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 MCLKE1 MCLKT1 2048 2048 2048 2048 2048 1544 1544 1544 1544 1544 2048 1544 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, along ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -49dB. See Figure ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. The jitter attenuator uses a data ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ARBITRARY PULSE GENERATOR FOR T1 AND E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE RANSMIT LOCK AND TCLK TPOS/TDATA or TNEG T SU TRANSMIT HDB3/B8ZS ENCODER The Encoder function is available in both Hardware and ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING outputs. Driver failure may be caused by a short circuit ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE ECEIVE QUALIZER EQC4 EQC3 EQC2 EQC1 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMIT AND RECEIVE TERMINATIONS The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide applications for T1, J1 and E1. ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 RXTSEL TERSEL1 TERSEL0 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 15. S IGURE IMPLIFIED ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T ABLE Table 11 summarizes the transmit terminations. TERSEL1 TERSEL0 100 Ω 110 Ω 0 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE IMPLIFIED B ackplane Interface P rim ary C ard T xT SEL=1, In ternal B ackup C ard T xT SEL=1, In ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The advantage of ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PATTERN TRANSMIT AND DETECT FUNCTION Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each channel can be independently programmed to transmit ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 transition of NLCD. The host has the option to ignore the request from the remote terminal respond to the request and manually activate Remote Loop-Back. ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR LOOP-BACK MODES The XRT83L34 supports several Loop-Back modes under both Hardware and Host control. In Hardware mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 REMOTE LOOP-BACK (RLOOP) With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR DIGITAL LOOP-BACK (DLOOP) Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/decoder and jitter ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 THE MICROPROCESSOR INTERFACE XRT83L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT83L34 is compatible with both the Intel-Asynchronous and ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 16: M ABLE ALE_AS Address Latch Enable/Address Strobe Input: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 16: M ABLE WR_R/W Write Strobe/Read-Write Operation Identifier: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then the following Microprocessor Interface pins will assume ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE The user can configure the Microprocessor Interface to operate in the Intel-Asynchronous Mode by tying the UPTS1 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Asynchronous" Mode Read Operation IGURE LLLUSTRATION OF AN NTEL Microprocessor places “target” Address value on A[6:0] ALE/AS A[6:0] CS* D[7:0] RD*/DS* WR*/R/W* RDY/DTACK* Address Decoding ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 the XRT83L34 device). In this case, the Microprocessor should continue to hold the "Write Strobe" (WR*/ R/W*) input pin "LOW" until it detects the "RDY*/DTACK*" output pin ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE _, THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE UMBER YPE N AME ALE/AS 71 ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 CONFIGURING THE MICROPROCESSOR ASYNCHRONOUS MODE The user can configure the Microprocessor Interface to operate in the Motorola-Asynchronous Mode by tying the UPTS1 (Pin 106) to the logic ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Asynchronous" READ Operation IGURE LLLUSTRATION OF A OTOROLA Microprocessor places “target” Address value on A[6:0] ALE/AS A[6:0] CS* D[7:0] RD*/DS* WR*/R/W* RDY/DTACK* Address Decoding Circuitry ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 8. After waiting the appropriate time for the data (on the bi-directional data bus) to settle and can be safely accepted by the Microprocessor, the XRT83L34 device ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR REGISTER TABLES The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit registers for independent programming and control. There are four additional registers ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 19: M ABLE DDRESS IT T YPE 9 0001001 R/W X Hex 0x09 10 0001010 R/W ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 19: M ABLE DDRESS IT T YPE 74 1001010 R/W Test byte 6 Hex 0x4A 75 1001011 R/W ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 MICROPROCESSOR REGISTER DESCRIPTIONS T 20: M ABLE EGISTER DDRESS HANNEL 0000000 C _0 HANNEL 0010000 C _1 HANNEL 0100000 C _2 HANNEL 0110000 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 21: M ABLE EGISTER DDRESS HANNEL 0000001 C _0 HANNEL 0010001 C _1 HANNEL 0100001 C _2 HANNEL 0110001 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 21: M ABLE D3 JASEL1_n Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator of each ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 22: M ABLE EGISTER DDRESS HANNEL 0000010 C _0 HANNEL 0010010 C _1 HANNEL 0100010 C _2 HANNEL 0110010 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 22: M ABLE D3 TXON_n Transmitter ON: Writing a “1” into this bit location turns on the Transmit Section of channel n. Writing a “0” shuts ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 23: M ABLE EGISTER DDRESS HANNEL 0000011 C _0 HANNEL 0010011 C _1 HANNEL 0100011 C _2 HANNEL 0110011 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 23: M ABLE D4 RXRES1_n Receive External Resistor Control Pin 1: In Host mode, this bit along with the RXRES0_n bit selects the value of the ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 24: M ABLE EGISTER DDRESS HANNEL 0000100 C _0 HANNEL 0010100 C _1 HANNEL 0100100 C _2 HANNEL 0110100 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 25: M ABLE EGISTER DDRESS HANNEL 0000101 C _0 HANNEL 0010101 C _1 HANNEL 0100101 C _2 HANNEL 0110101 C _3 HANNEL ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 25: M ABLE D3 NLCD_n Network Loop-Code Detection: This bit operates differently in the Manual or the Automatic Network Loop-Code detection modes. In the Manual Loop-Code detection mode, ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 26: M ABLE EGISTER DDRESS HANNEL 0000110 C _0 HANNEL 0010110 C _1 HANNEL 0100110 C _2 HANNEL 0110110 C _3 HANNEL ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 27: M ABLE EGISTER DDRESS HANNEL 0000111 C _0 HANNEL 0010111 C _1 HANNEL 0100111 C _2 HANNEL 0110111 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 28: M ABLE EGISTER DDRESS HANNEL 0001000 C _0 HANNEL 0011000 C _1 HANNEL 0101000 C _2 HANNEL 0111000 C _3 HANNEL ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 30: M ABLE EGISTER DDRESS HANNEL 0001010 C _0 HANNEL 0011010 C _1 HANNEL 0101010 C _2 HANNEL 0111010 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 32: M ABLE EGISTER DDRESS HANNEL 0001100 C _0 HANNEL 0011100 C _1 HANNEL 0101100 C _2 HANNEL 0111100 C _3 HANNEL ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 34: M ABLE EGISTER DDRESS HANNEL 0001110 C _0 HANNEL 0011110 C _1 HANNEL 0101110 C _2 HANNEL 0111110 C _3 HANNEL B # ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 36: M ABLE R A EGISTER DDRESS 1000000 N AME SR/DR Single-rail/Dual-rail Select: Writing a “1” to this bit configures all 8 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CLOCK SELECT REGISTER The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 37: M ABLE R A EGISTER DDRESS 1000001 N AME E1arben E1 Arbitrary Pulse Enable This bit is used to enable the ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 37: M ABLE D2 RXMUTE Receive Output Mute: Writing a “1” to this bit, mutes receive outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for any ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 T 38: M ABLE D3 SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slic- ing level for the slicer per the following ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ELECTRICAL CHARACTERISTICS Storage Temperature...................-65° 150°C Operating Temperature.............-40° 85°C Supply Voltage..........................- ABLE VDD=3.3V±5%, P ARAMETER Power Supply ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE VDD=3.3V±5%, P ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 43 ABLE VDD=3.3V±5%, P ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Receiver Sensitivity ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE VDD=3.3V±5%, P ARAMETER AMI Output Pulse Amplitude Application W 120 Application Output Pulse Width Output Pulse Width Ratio Output Pulse ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 30. ITU G.703 P IGURE V = 100% 50 ABLE Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 F 31. DSX IGURE ULSE EMPLATE T 48: DSX1 I ABLE M INIMUM CURVE T (UI) N IME ORMALIZED AMPLITUDE -0.77 -0.23 -0.23 -0.15 0.0 ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE VDD=3.3V±5 ARAMETER E1 MCLK Clock Frequency T1 MCLK Clock Frequency MCLK Clock Duty Cycle MCLK Clock Tolerance TCLK Duty Cycle Transmit Data Setup Time Transmit ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE ECEIVE LOCK AND UTPUT R DY RCLK RPOS or RNEG MICROPROCESSOR INTERFACE I/O TIMING NTEL NTERFACE ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 50: A ABLE SYNCHRONOUS S YMBOL t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 OTOROLA SYCHRONOUS NTERFACE The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select ...

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ORDERING INFORMATION P N ART UMBER XRT83L34IV PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE 102 103 128 Note: The control dimensions are ...

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XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 REVISIONS R EVISION A1.0.1 Advanced Versions thru A1.0.7 P1.1.0 Preliminary release version P1.2.0 Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Micropro- ...

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... QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...