XRT83L34ES Exar, XRT83L34ES Datasheet - Page 84

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
R
EGISTER
1000001
B
D7
D6
D5
D4
D3
IT
A
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
#
DDRESS
MCLKRATE Master clock Rate Select: The state of this bit programs the
CLKSEL2
CLKSEL1
CLKSEL0
E1arben
N
AME
T
ABLE
37: M
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
Clock Select Inputs for Master Clock Synthesizer bit 2:
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
Clock Select inputs for Master Clock Synthesizer bit 1:
Clock Select inputs for Master Clock Synthesizer bit 0:
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
See description of bit D6 for function of this bit.
See description of bit D6 for function of this bit.
M CLKE1
2048
2048
2048
1544
1544
2048
kHz
128
128
256
256
16
16
56
56
64
64
8
8
ICROPROCESSOR
M CLKT1
2048
2048
1544
1544
1544
1544
kHz
X
X
X
X
X
X
X
X
X
X
X
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R
81
EGISTER
CLKSEL1
F
UNCTION
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
#65, B
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IT
M CLKRATE
D
ESCRIPTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKOUT/
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
kHz
R
EGISTER
xr
T
R/W
R/W
R/W
R/W
R/W
YPE
R
V
ALUE
ESET
0
0
0
0
0