XRT83L34ES Exar, XRT83L34ES Datasheet - Page 45

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XRT83L34ES

Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet

Specifications of XRT83L34ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
xr
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L34 are described separately.
TRANSMIT
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68µF capacitor is used in series with TTIP for blocking DC bias. See
of the transmit section for an N+1 redundancy scheme.
N
OTE
F
: For simplification, the over voltage protection circuitry was omitted.
IGURE
18. S
Backplane Interface
IMPLIFIED
T xT S EL =1, Internal
Prim ary C ard
T xT S EL =1, Internal
P rim ary C ard
T xT S EL =1, Internal
B ackup C ard
T xT S EL=1, Inte rnal
P rim ary C ard
B
LOCK
D
IAGRAM
Tx
Tx
Tx
Tx
XR T83L34
X R T83L34
X R T83L34
X R T83L4
0.68
0.68
0.68
- T
0.68
RANSMIT
µ
µ
µ
µ
F
F
F
F
42
S
ECTION FOR
Line Interface C ard
N+1 R
Figure 18
1:2 or 1:2.45
1:2 or 1:2.45
1:2 or 1:2.45
EDUNDANCY
for a simplified block diagram
T1/E 1 Line
T1/E 1 Line
T1/E1 Line
XRT83L34
REV. 1.0.1

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