XRT83L34ES Exar, XRT83L34ES Datasheet - Page 6

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
THE MICROPROCESSOR INTERFACE............................................................................ 49
TRANSMITTER (C
REDUNDANCY APPLICATIONS ............................................................................................................... 39
TYPICAL REDUNDANCY SCHEMES ....................................................................................................... 40
P
T
N
T
L
L
R
D
D
THE PINS OF THE MICROPROCESSOR INTERFACE
OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL
C
THE INTEL
T
O
T
MOTOROLA
CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE MOTOROLA
THE MOTOROLA
T
M
.................................................................................................................................................................... 56
OOP
OCAL
ATTERN
RANSMIT
RANSMIT AND
HE INTEL
ABLE
HE
ETWORK
EMOTE
IGITAL
UAL
ONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL
PERATING THE
ICROPROCESSOR
T
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .............. 37
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) .................... 38
T
T
T
T
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ........ 41
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............... 41
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy .......................... 42
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ............................ 43
T
T
T
T
Figure 20. Local Analog Loop-back signal flow............................................................................. 46
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path .................. 47
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path ............... 47
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................. 48
Figure 24. Signal flow in Dual loop-back mode.............................................................................. 48
T
T
Figure 25. Illlustration of an Intel-Asynchronous Mode Read Operation .................................... 54
Figure 26. Illustration of an Intel-Asynchronous Mode Write Operation ..................................... 55
Figure 27. Illlustration of a Motorola-Asynchronous Mode Read Operation............................... 58
Figure 28. Illustration of a Motorola-Asynchronous Write Operation.......................................... 59
M
-B
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
L
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
OTOROLA
_, T
A
OOP
ACK
L
Transmit Termination Mode ........................................................................................................................ 38
External Transmit Termination Mode .......................................................................................................... 38
NALOG
L
OOP
T
-
-
OOP
ASYNCHRONOUS READ CYCLE
A
L
ASYNCHRONOUS WRITE CYCLE
-
HE
RANSMIT AND
7: R
8: T
9: T
10: T
11: T
12: P
13: L
14: L
15: L
-B
16: M
17: T
ASYNCHRONOUS MODE
OOP
LL
M
ERATE IN THE
-B
ACK
R
ODES
-B
O
D
-
L
OLES OF VARIOUS MICROPROCESSOR INTERFACE PINS
ASYNCHRONOUS READ
-
ACK
RANSMIT
ERMINATION
M
ECEIVE
ASYNCHRONOUS WRITE CYCLE
NES
C
ETECT
ACK
OOP
RANSMIT
RANSMIT
OOP
OOP
OOP
HE
ATTERN TRANSMISSION CONTROL
ICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
........................................................................................................................................ 48
ODE
ICROPROCESSOR
R
...................................................................................................................................... 46
HANNELS
(DLOOP) ..................................................................................................................... 48
R
EGISTER
(TAOS) ....................................................................................................................... 44
-B
(RLOOP) .................................................................................................................... 47
-C
-
-
BACK CONTROL IN
BACK CONTROL IN
OLES OF THE
D
Q
ACK
T
ODE
D
ETECTION AND
T
ERMINATIONS
UASI
ETECT
I
ERMINATION
T
T
NTEL
ERMINATION
ERMINATIONS
(ALOOP).......................................................................................................... 46
S
D
0 - 3) .............................................................................................................. 38
-R
T
ELECT
ETECTION
ABLES
-A
ANDOM
F
................................................................................................................ 56
SYNCHRONOUS
UNCTION
IN
V
C
ARIOUS
-
.......................................................................................................... 60
TERFACE IN THE
CYCLE
ONTROL
........................................................................................................ 37
C
T
S
....................................................................................................... 53
...................................................................................................... 54
C
C
RANSMISSION
H
H
ONTROL
IGNAL
.................................................................................................... 39
ONTROL
ONTROL
ARDWARE MODE
OST MODE
................................................................................................. 44
:..............................................................................................57
M
............................................................................................. 58
............................................................................................ 38
............................................................................................ 49
ICROPROCESSOR
S
OURCE
........................................................................................ 38
M
....................................................................................... 44
...................................................................................... 39
...................................................................................... 44
ODE
II
................................................................................... 46
................................................................................. 44
M
.............................................................................. 52
OTOROLA
(TDQRSS) ........................................................... 45
-
......................................................................... 46
ASYNCHRONOUS MODE
I
NTERFACE
-A
............................................................ 49
SYNCHRONOUS
,
WHEN CONFIGURED TO OPERATE IN THE
-
ASYNCHRONOUS
P
INS
-
ASYNCHRONOUS MODE
,
...................................... 52
WHEN CONFIGURED TO OP
M
ODE
.......................... 55
M
xr
ODE
.............. 53
....... 57
-