XRT83L34ES Exar, XRT83L34ES Datasheet - Page 22

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XRT83L34ES

Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet

Specifications of XRT83L34ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
XRT83L34
REV. 1.0.1
JITTER ATTENUATOR
S
IGNAL
JASEL0
JASEL1
A[6]
A[5]
N
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
AME
P
58
57
57
58
IN
#
T
YPE
I
Jitter Attenuator Select Pins - Hardware Mode
Jitter Attenuator select pin 0
Jitter Attenuator select pin 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path,
the receive path or to disable it.
Microprocessor Address Bits A[6:5] -Host Mode
See “Address Bus Input Pins/Jitter Attenuator Select Input Pins/
Equalizer Control Input pins:” on page 18.
N
OTE
: Internally pulled “Low” with a 50kΩ resistor.
JASEL1
JASEL1
0
0
0
0
0
1
0
1
19
JASEL0
JASEL0
0
0
0
1
1
0
1
1
Disabled
Disabled
Transmit
Transmit
JA Path
JA Path
Receive
Receive
Receive
Receive
D
ESCRIPTION
-----
T1
T1
JA BW Hz
3
3
3
3
3
3
JA BW
MHz
-----
1.5
1.5
E1
E1
10
10
10
10
xr
FIFO Size
FIFO Size
T1/E1
--------
32/32
32/32
32/32
32/32
64/64
64/64

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