XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 26

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
The jitter attenuator reduces phase and frequency jitter in the recovered clock if it is selected in the receive
path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If
the LIU is used for line synchronization (loop timing systems), the JA should be enabled in the receive path.
When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth
of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is
outside the 2-Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the
bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The
JA has a clock delay equal to ½ of the FIFO bit depth.
N
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with 000V or B00V, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with 000VB0VB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
The digital output data can be programmed to either single rail or dual rail formats.
diagram of a repeating "0011" pattern in single-rail mode.
pattern in dual rail mode.
F
F
3.3
3.4
3.4.0.1
OTE
IGURE
IGURE
: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the jitter attenuator
can be selected in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
RNEG
10. S
RPOS
11. D
RPOS
RCLK
RCLK
Jitter Attenuator
HDB3/B8ZS Decoder
INGLE
UAL
RPOS/RNEG/RCLK
R
AIL
R
AIL
M
M
ODE
ODE
0
0
W
W
ITH A
ITH A
F
IXED
F
IXED
R
0
0
EPEATING
R
EPEATING
23
"0011" P
"0011" P
1
1
Figure 11
ATTERN
ATTERN
is a timing diagram of the same fixed
1
1
Figure 10
0
0
is a timing
REV. 1.0.1