XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 74
XRT83VSH314ES
Manufacturer Part Number
XRT83VSH314ES
Description
Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
Manufacturer
Exar
Datasheet
1.XRT83VSH314ES.pdf
(80 pages)
Specifications of XRT83VSH314ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
D[7:1]
B
B
B
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
IT
IT
IT
Device "ID" The device "ID" of the XRT83VSH314 short haul LIU is 0xF2h.
Reserved
E1Arben
Revision
N
N
N
"ID"
AME
AME
AME
T
T
ABLE
ABLE
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for shap-
ing the transmit pulse shape when E1 mode is selected. If this bit
is set to "1", all 14 channels will be configured for the Arbitrary
Mode. However, each channel is individually controlled by pro-
gramming the channel registers 0xn8 through 0xnF, where n is the
number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
Along with the revision "ID", the device "ID" is used to enable soft-
ware to identify the silicon adding flexibility for system control and
debug.
The revision "ID" of the XRT83VSH314 LIU is used to enable soft-
ware to identify which revision of silicon is currently being tested.
The revision "ID" for the first revision of silicon will be 0x01h.
N
OTE
: The value contained in this register is subject to change
54: M
55: M
when a newer revision of the silicon has been issued.
ICROPROCESSOR
ICROPROCESSOR
E1 A
T
ABLE
R
RBITRARY
D
EVISION
EVICE
53: E1 A
"ID" R
"ID" R
S
F
F
F
ELECT
UNCTION
UNCTION
UNCTION
R
R
71
EGISTER
RBITRARY
EGISTER
EGISTER
EGISTER
R
EGISTER
(0
(0
0
0
X
S
X
X
X
FE
FE
FF
FF
ELECT
(0
H
H
H
X
H
)
)
F4
B
B
H
IT
IT
)
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Register
Type
Type
Type
R/W
RO
RO
(HW reset)
(HW reset)
(HW reset)
REV. 1.0.1
Default
Default
Default
Value
Value
Value
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
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