IS42S16800D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16800D-7TL Datasheet - Page 2
![IC SDRAM 128MBIT 143MHZ 54TSOP](/photos/7/23/72310/is42s16800d-7tl_sml.jpg)
IS42S16800D-7TL
Manufacturer Part Number
IS42S16800D-7TL
Description
IC SDRAM 128MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7TL
Package / Case
54-TSOP II
Memory Size
128M (8Mx16)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1020
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16800D-7TL
Manufacturer:
ISSI
Quantity:
20
Company:
Part Number:
IS42S16800D-7TL
Manufacturer:
ISSI
Quantity:
240
Part Number:
IS42S16800D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS42S16800D-7TLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS42S16800D-7TLI
Manufacturer:
ISSI
Quantity:
20 000
IS42S81600D,
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
and 3.3V V
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows
by 1,024 columns by 8 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
2
CKE
RAS
CAS
A10
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DDQ
memory systems containing 134,217,728
GENERATOR
COMMAND
DECODER
12
CLOCK
&
ADDRESS
LATCH
ROW
IS42S16800D
9
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
12
12
CONTROLLER
REFRESH
COUNTER
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
SELF
DD
ROW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
Integrated Silicon Solution, Inc. — www.issi.com
12
4096
16
16
4096
4096
4096
DATA OUT
BUFFER
BUFFER
9
DATA IN
(x 16)
COLUMN DECODER
512
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
2
DQML
DQMH
DQ 0-15
V
V
DD
ss
/V
/V
ss
DDQ
Q
07/28/08
Rev. E