IS42S16800D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16800D-7TL Datasheet - Page 20
![IC SDRAM 128MBIT 143MHZ 54TSOP](/photos/7/23/72310/is42s16800d-7tl_sml.jpg)
IS42S16800D-7TL
Manufacturer Part Number
IS42S16800D-7TL
Description
IC SDRAM 128MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7TL
Package / Case
54-TSOP II
Memory Size
128M (8Mx16)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1020
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IS42S81600D,
FUNCTIONAL DESCRIPTION
The 128Mb SDRAMs are quad-bank DRAMs which operate
at 3.3V and include a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits or 4,096 rows by 1,024
columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-A11 select the row).
The address bits A0-A9 (x8); A0-A8 (x16) registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
20
IS42S16800D
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 128M SDRAM is initialized after the power is applied to
V
DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle state
after which at least two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an un-
known state.
DD
and V
Integrated Silicon Solution, Inc. — www.issi.com
DDQ
(simultaneously) and the clock is stable with
07/28/08
Rev. E