IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 14

• Manufacturer Part Number: IS42S32800B-7BL
• Description: IC SDRAM 256MBIT 143MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800B-7BL

• Package / Case: 90-BGA
• Memory Size: 256M (8Mx32)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 32 bit
• Organization: 2 Mbit x 32
• Maximum Clock Frequency: 143 MHz
• Access Time: 7 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1024

IS42S32800B
14
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank
WRITE with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE
to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE
to bank m.
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
COMMAND
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
NOP
T0
Page Active
T0
NOP
WRITE - AP
BANK n,
Page Active
BANK n
COL a
T1
D
a
WRITE - AP
IN
BANK n,
WRITE with Burst of 4
Page Active
BANK n
COL a
T1
D
a
IN
WRITE with Burst of 4
a + 1
T2
D
NOP
IN
a + 1
T2
D
NOP
IN
a + 2
T3
D
IN
BANK m,
READ - AP
T3
COL d
BANK m
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
Interrupt Burst, Write-Back
d
t
IN
WR - BANK n
T4
WRITE with Burst of 4
NOP
T5
d + 1
NOP
D
T5
IN
NOP
Precharge
t
RP - BANK n
T6
d + 2
NOP
Precharge
D
t RP - BANK n
IN
T6
D
NOP
OUT
d
DON’T CARE
Integrated Silicon Solution, Inc.
DON’T CARE
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
T7
D
d + 1
NOP
t RP - BANK m
OUT
I
®
07/21/09
Rev. F