IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 22

• Manufacturer Part Number: IS42S32800B-7BL
• Description: IC SDRAM 256MBIT 143MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800B-7BL

• Package / Case: 90-BGA
• Memory Size: 256M (8Mx32)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 32 bit
• Organization: 2 Mbit x 32
• Maximum Clock Frequency: 143 MHz
• Access Time: 7 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1024

E
IS42S32800B
22
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
* CL is CAS# Latency.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RRD
RCD
RP
RAS
CK2
CK3
OH
CH
CL
IS
IH
LZ
HZ
WR
CCD
MRS
AC
tCK and tRC.Input signals are changed one time during tCK.
AC Electrical Characteristics (Recommended Operating Conditions)
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to precharge time
(same bank)
Clock cycle time
Access time from CLK
(positive edge)
Data output hold time
Clock high time
Clock low time
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Data output low impedance
Data output high impedance
Write Recovery Time
CAS# to CAS# Delay time
Mode Register Set cycle time
A.C. Parameter
CL* = 2
CL* = 3
2.5/2.5
7.5/10
2.5/2.5
2.0/2.0
60/70
18/20
12/14
42/45
18/20
Min.
2/2.5
6/7
1
1
2
1
2
- 6/7
Integrated Silicon Solution, Inc.
120,000
5.5/5.5
Max.
5.4
5,6,7,8
Unit
CLK
ns
Note
10
10
10
10
9
9
9
9
9
9
9
8
07/21/09
9
Rev. F