IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 15

IC SDRAM 256MBIT 143MHZ 90BGA

IS42S32800B-7BL

Manufacturer Part Number
IS42S32800B-7BL
Description
IC SDRAM 256MBIT 143MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S32800B-7BL

Package / Case
90-BGA
Memory Size
256M (8Mx32)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
32 bit
Organization
2 Mbit x 32
Maximum Clock Frequency
143 MHz
Access Time
7 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
150 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
BGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1024

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IS42S32800B
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
7
Mode Register Set command
(RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A11-A0 =Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set
command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make
SDRAM useful for a variety of different applications.The default values of the Mode Register after power-up are
undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and
A11~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write
in the mode register (refer to the following figure).The contents of the mode register can be changed using the
same command and the clock cycle requirements during operation as long as all banks are in the idle state.
15

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