C8051T323-GMR Silicon Labs, C8051T323-GMR Datasheet
C8051T323-GMR
Specifications of C8051T323-GMR
Related parts for C8051T323-GMR
C8051T323-GMR Summary of contents
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Analog Peripherals - 10-Bit ADC (‘T620/320/321 only) • 500 ksps • external inputs • VREF from on-chip VREF, external pin, Internal 1.8 V Regulator • Internal or external start of conversion source ...
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C8051T620/621/320/321/322/323 2 Rev. 1.1 ...
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Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 20 3. Pin Definitions.......................................................................................................... 21 4. LQFP-32 Package Specifications ........................................................................... 27 5. QFN-32 Package Specifications ............................................................................. 29 6. QFN-28 Package Specifications ............................................................................. 31 7. Electrical Characteristics ........................................................................................ 33 ...
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C8051T620/621/320/321/322/323 15.2.1.2. Bit Addressable Locations .............................................................. 87 15.2.1.3. Stack ............................................................................................ 87 15.2.2. External RAM .......................................................................................... 88 15.2.3. Accessing USB FIFO Space ................................................................... 88 16. Special Function Registers................................................................................... 91 17. Interrupts ................................................................................................................ 96 17.1. MCU Interrupt Sources and Vectors................................................................ 96 17.1.1. ...
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External Oscillator Drive Circuit..................................................................... 129 21.6.1. External Crystal Mode........................................................................... 129 21.6.2. External RC Example............................................................................ 131 21.6.3. External Capacitor Example.................................................................. 131 22. Port Input/Output ................................................................................................. 133 22.1. Port I/O Modes of Operation.......................................................................... 134 22.1.1. Port Pins Configured for Analog I/O...................................................... ...
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C8051T620/621/320/321/322/323 24.3.1. Transmitter Vs. Receiver....................................................................... 190 24.3.2. Arbitration.............................................................................................. 190 24.3.3. Clock Low Extension............................................................................. 190 24.3.4. SCL Low Timeout.................................................................................. 190 24.3.5. SCL High (SMBus Free) Timeout ......................................................... 191 24.4. Using the SMBus........................................................................................... 191 24.4.1. SMBus Configuration Register.............................................................. 191 24.4.2. SMB0CN Control ...
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Mode 1: 16-bit Counter/Timer ............................................................... 243 28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 243 28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 244 28.2. Timer 2 .......................................................................................................... 250 28.2.1. 16-bit Timer with Auto-Reload............................................................... 250 28.2.2. 8-bit Timers with ...
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C8051T620/621/320/321/322/323 List of Figures Figure 1.1. C8051T620/1 Block Diagram ................................................................ 16 Figure 1.2. C8051T320/2 Block Diagram ................................................................ 17 Figure 1.3. C8051T321/3 Block Diagram ................................................................ 18 Figure 1.4. Typical Bus-Powered Connections ....................................................... 19 Figure 3.1. QFN-32 Pinout Diagram (Top View) ..................................................... ...
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C8051T620/621/320/321/322/323 Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 138 Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 139 Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 140 Figure 23.1. USB0 Block Diagram ......................................................................... 155 Figure ...
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C8051T620/621/320/321/322/323 Figure 28.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 252 Figure 28.7. Timer 3 16-Bit Mode Block Diagram ................................................. 256 Figure 28.8. Timer 3 8-Bit Mode Block Diagram ................................................... 257 Figure 28.9. Timer 3 Low-Frequency Oscillation Capture ...
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List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 47 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 48 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 48 SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 49 SFR ...
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C8051T620/621/320/321/322/323 SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control ................................... 128 SFR Definition 21.6. OSCXCN: External Oscillator Control ........................................ 132 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 .......................................... 142 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 ...
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SFR Definition 28.2. TCON: Timer Control ................................................................. 246 SFR Definition 28.3. TMOD: Timer Mode ................................................................... 247 SFR Definition 28.4. TL0: Timer 0 Low Byte ............................................................... 248 SFR Definition 28.5. TL1: Timer 1 Low Byte ............................................................... 248 SFR Definition 28.6. TH0: ...
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C8051T620/621/320/321/322/323 List of Tables Table 2.1. Product Selection Guide ......................................................................... 20 Table 3.1. Pin Definitions for the C8051T620/621/320/321/322/323 ....................... 21 Table 7.1. Absolute Maximum Ratings .................................................................... 33 Table 7.2. Global Electrical Characteristics ............................................................. 34 Table 7.3. Port I/O DC Electrical ...
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System Overview C8051T620/621/320/321/322/323 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ( MIPS) ...
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C8051T620/621/320/321/322/323 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory C2CK/RST Debug / Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator GND System Clock ...
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C8051T620/621/320/321/322/323 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator Core Power GND ...
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C8051T620/621/320/321/322/323 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator Core Power GND ...
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SUPPLY NET Add decoupling/bypass 4.7µF capacitors close to each voltage supply pin. USB Add ESD protection diodes designed for use with USB, such as Littlefuse SP0503BAHT or equivalent. Keep the USB shield ground isolated from the device ground. *Note : ...
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... C8051T320-GQ 48 16k 1280 C8051T321-GM 48 16k 1280 C8051T322-GQ 48 16k 1280 C8051T323-GM 48 16k 1280 Y Notes: 1. 512 Bytes Reserved for Factory use. 2. Pin compatible with the C8051F320-GQ. 3. Pin compatible with the C8051F321-GM. 4. Lead plating material is 100% Matte Tin (Sn ...
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Pin Definitions Table 3.1. Pin Definitions for the C8051T620/621/320/321/322/323 Pin Number Name ‘T620/1 ‘T320/2 ‘T321 GND RST C2CK P3. C2D REGIN VBUS ...
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C8051T620/621/320/321/322/323 Table 3.1. Pin Definitions for the C8051T620/621/320/321/322/323(Continued) Pin Number Name ‘T620/1 ‘T320/2 ‘T321/3 P0. XTAL2 P0 P0 P0. CNVSTR P0. VREF P1 ...
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Table 3.1. Pin Definitions for the C8051T620/621/320/321/322/323(Continued) Pin Number Name ‘T620/1 ‘T320/2 ‘T321/3 P1 P2.3 ...
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C8051T620/621/320/321/322/323 P0.1 1 P0.0 2 GND VIO 6 VDD 7 REGIN 8 Figure 3.1. QFN-32 Pinout Diagram (Top View) 24 C8051T620/1-GM Top View GND (optional) Rev. 1.1 24 P1.2 23 P1.3 22 P1.4 21 P1.5 ...
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C8051T620/621/320/321/322/323 1 P0.1 2 P0.0 3 GND C8051T320/2- Top View 5 D- VDD 6 7 REGIN VBUS 8 Figure 3.2. LQFP-32 Pinout Diagram (Top View Rev. 1.1 P1.2 P1.3 P1.4 ...
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C8051T620/621/320/321/322/323 P0.1 1 P0.0 2 GND 3 C8051T321/3- VDD 6 REGIN 7 Figure 3.3. QFN-28 Pinout Diagram (Top View) 26 Top View GND (optional) Rev. 1.1 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 ...
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LQFP-32 Package Specifications Figure 4.1. LQFP-32 Package Drawing Table 4.1. LQFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.80 ...
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C8051T620/621/320/321/322/323 Figure 4.2. LQFP-32 Recommended PCB Land Pattern Table 4.2. LQFP-32 PCB Land Pattern Dimensions Dimension Min C1 8.40 C2 8.40 E 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern ...
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QFN-32 Package Specifications Figure 5.1. QFN-32 Package Drawing Table 5.1. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.20 3.30 e 0.50 BSC. E 5.00 BSC. Notes: 1. ...
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C8051T620/621/320/321/322/323 Figure 5.2. QFN-32 Recommended PCB Land Pattern Table 5.2. QFN-32 PCB Land Pattern Dimensions Dimension Min C1 4.80 C2 4.80 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. ...
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QFN-28 Package Specifications Figure 6.1. QFN-28 Package Drawing Table 6.1. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 ...
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C8051T620/621/320/321/322/323 Figure 6.2. QFN-28 Recommended PCB Land Pattern Table 6.2. QFN-28 PCB Land Pattern Dimensions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during program- PP ming) with respect to GND Voltage on V ...
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C8051T620/621/320/321/322/323 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Supply Voltage (Note 1) Regulator1 in Normal Mode Regulator1 in Bypass Mode Digital Supply Current with CPU V ...
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Table 7.3. Port I/O DC Electrical Characteristics V = 1 < –40 to +85 °C unless otherwise specified Parameters Conditions Output High Voltage I = –10 µA, Port I/O push-pull OH ...
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C8051T620/621/320/321/322/323 Table 7.5. Internal Voltage Regulator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions Voltage Regulator (REG0 Input Voltage Range 2 Output Voltage (V ) Output Current = 1 to 100 Output ...
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Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Conditions Oscillator Frequency IFCN = 11b Oscillator Supply Current 25 °C, ...
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C8051T620/621/320/321/322/323 Table 7.10. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz ...
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Table 7.11. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameter Conditions Linearity Slope Slope Error* Offset Temp = 0 °C Offset Error* Temp = 0 °C Note: Represents one standard ...
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C8051T620/621/320/321/322/323 Table 7.13. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Conditions Response Time: CP0+ – CP0– = 100 mV * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 ...
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Table 7.14. USB Transceiver Electrical Characteristics 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Conditions Transmitter Output High Voltage ( Output Low Voltage ( Output Crossover Point (V ...
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C8051T620/621/320/321/322/323 7.3. Typical Performance Curves 12.0 10.0 8.0 6.0 4.0 2.0 0 Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 7.2. Idle ...
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ADC (ADC0, C8051T620/320/321 only) ADC0 on the C8051T620/320/321 is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window detector. The ADC is fully configurable under ...
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C8051T620/621/320/321/322/323 8.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. ...
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Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at ...
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C8051T620/621/320/321/322/323 8.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling ...
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SFR Definition 8.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following ...
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C8051T620/621/320/321/322/323 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits ...
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SFR Definition 8.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ...
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C8051T620/621/320/321/322/323 8.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ...
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C8051T620/621/320/321/322/323 8.4.1. Window Detector Example Figure 8.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit ...
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ADC0 Analog Multiplexer (C8051T620/320/321 only) ADC0 on the C8051T620/320/321 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2, P3.0 and some ...
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C8051T620/621/320/321/322/323 SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 1 0 Reset SFR Address = 0xBB Bit Name 7:5 UNUSED Unused. Read = 100b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input ...
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Temperature Sensor (C8051T620/320/321 only) An on-chip temperature sensor is included on the C8051T620/320/321 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should ...
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C8051T620/621/320/321/322/323 9.1. Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 7.11 on page 39 for specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. A single-point offset measurement ...
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Voltage Reference Options The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply volt- age ( ...
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C8051T620/621/320/321/322/323 SFR Definition 10.1. REF0CN: Reference Control Bit 7 6 REFBGS Name R/W R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7 REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain for the ...
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Voltage Regulators (REG0 and REG1) C8051T620/621/320/321/322/323 devices include two internal voltage regulators: one regulates a voltage source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 V from a V supply of ...
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C8051T620/621/320/321/322/323 VBUS From VBUS From 5 V REGIN Power Net VDD Power Net Figure 11.2. REG0 Configuration: USB Self-Powered VBUS From VBUS REGIN From 3 V Power Net Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled 60 ...
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C8051T620/621/320/321/322/323 VBUS From 5 V REGIN Power Net VDD Power Net Figure 11.4. REG0 Configuration: No USB Connection VBUS Sense Voltage Regulator (REG0 Out Rev. 1.1 Device Power Net 61 ...
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C8051T620/621/320/321/322/323 11.2. Voltage Regulator (REG1) Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode. This allows any enabled reset source to generate a reset for the device and bring the device out of ...
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SFR Definition 11.1. REG01CN: Voltage Regulator Control Bit 7 6 REG0DIS VBSTAT Reserved Name R/W R Type 0 0 Reset SFR Address = 0xC9 Bit Name 7 REG0DIS Voltage Regulator (REG0) Disable. This bit enables or disables the REG0 Voltage ...
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C8051T620/621/320/321/322/323 12. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...
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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “30. C2 Interface” on page 282. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys- tem device programming and debugging ...
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C8051T620/621/320/321/322/323 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic ORL A, direct OR direct byte to A ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct direct byte ORL direct, ...
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C8051T620/621/320/321/322/323 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative MOVX A, @Ri Move ...
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Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ rel Jump if ...
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C8051T620/621/320/321/322/323 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...
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SFR Definition 12.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x82 Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. SFR Definition ...
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C8051T620/621/320/321/322/323 SFR Definition 12.3. SP: Stack Pointer Bit 7 6 Name Type Reset 0 0 SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer ...
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SFR Definition 12.6. PSW: Program Status Word Bit 7 6 Name CY AC Type R/W R/W Reset 0 0 SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted ...
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C8051T620/621/320/321/322/323 13. Prefetch Engine The C8051T620/621/320/321/322/323 family of devices incorporate a 2-byte prefetch engine. Because the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for ...
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Comparator0 and Comparator1 C8051T620/621/320/321/322/323 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 14.1, Comparator1 is shown in Figure 14.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described ...
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C8051T620/621/320/321/322/323 CP1 + Comparator CP1 - Input Mux CPT1MD Figure 14.2. Comparator1 Functional Block Diagram The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, ...
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CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 14.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator ...
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C8051T620/621/320/321/322/323 SFR Definition 14.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 ...
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SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. ...
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C8051T620/621/320/321/322/323 SFR Definition 14.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. 6 CP1OUT Comparator1 ...
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SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9C Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 Rising-Edge Interrupt Enable. ...
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C8051T620/621/320/321/322/323 14.1. Comparator Multiplexers C8051T620/621/320/321/322/323 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 14.5 and SFR Definition 14.6). The CMXnP2–CMXnP0 bits select ...
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SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[2:0] Name R Type 0 0 Reset SFR Address = 0x9F Bit Name 7 Unused Unused. Read = 0b; Write = don’t care. 6:4 CMX0N[2:0] Comparator0 Negative Input MUX Selection. ...
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C8051T620/621/320/321/322/323 SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection Bit 7 6 CMX1N[2:0] Name R Type 0 0 Reset SFR Address = 0x9E Bit Name 7 Unused Unused. Read = 0b; Write = don’t care. 6:4 CMX1N[2:0] Comparator1 Negative Input MUX ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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... C8051T621 C8051T320 C8051T321 C8051T322 C8051T323 15.1.2. Temperature Offset Calibration The C8051T620/621/320/321/322/323 devices include a factory calibrated temperature sensor offset coef- ficient located in the EPROM memory. The TOFFH and TOFFL values are located at 0x3FFB and 0x3FFA, respectively. More information on using the temperature sensor calibration values can be found in Section “ ...
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Data Memory The C8051T620/621/320/321/322/323 device family includes 1280 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. 1024 bytes of this memory is on-chip “external” memory. The data ...
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C8051T620/621/320/321/322/323 15.2.2. External RAM There are 1024 bytes of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX ...
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XRAM space at addresses 0x0400 to 0x07FF. The normal on-chip XRAM at the same addresses can- not be accessed when the USBFAE bit is set to 1. Important Note: The USB clock must be active when accessing FIFO space. ...
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C8051T620/621/320/321/322/323 SFR Definition 15.2. EMI0CF: External Memory Configuration Bit 7 6 USBFAE Name R R/W Type 0 0 Reset SFR Address = 0x85 Bit Name 7 Unused Unused. Read = 0b; Write = Don’t Care 6 USBFAE USB FIFO Access ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T620/621/320/321/322/323's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...
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C8051T620/621/320/321/322/323 Table 16.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ADC0 Greater-Than ...
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Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xB3 Internal Oscillator Calibration OSCICL 0xB2 Internal Oscillator Control OSCICN 0x86 Low-Frequency Oscillator Control OSCLCN 0xB1 External Oscillator Control OSCXCN ...
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C8051T620/621/320/321/322/323 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xDB PCA Module 1 Mode Register PCA0CPM1 0xDC PCA Module 2 Mode Register PCA0CPM2 0xDD PCA Module 3 Mode ...
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Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0x8C Timer/Counter 0 High TH0 0x8D Timer/Counter 1 High TH1 0x8A Timer/Counter 0 Low TL0 0x8B Timer/Counter 1 Low TL1 ...
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C8051T620/621/320/321/322/323 17. Interrupts The C8051T620/621/320/321/322/323 include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripher- als and external inputs pins varies according to the specific version ...
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Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior- ity order is used to ...
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C8051T620/621/320/321/322/323 Table 17.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B USB0 ...
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SFR Definition 17.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. ...
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C8051T620/621/320/321/322/323 SFR Definition 17.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1b, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface ...
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SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer ...
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C8051T620/621/320/321/322/323 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of ...
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SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xE7 Bit Name 7:4 Unused Unused. Read = 0000b, Write = Don't Care. 3 EMAT Enable Port Match Interrupts. ...
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C8051T620/621/320/321/322/323 SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xF7 Bit Name 7-4 Unused Unused. Read = 0000b, Write = Don't Care. 3 PMAT Port Match Interrupt ...
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INT0 and INT1 External Interrupt Sources The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...
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C8051T620/621/320/321/322/323 SFR Definition 17.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. ...
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Program Memory (EPROM) C8051T620/621/320/321/322/323 devices include on-chip byte-programmable EPROM for pro- gram code storage. The EPROM memory can be programmed via the C2 debug and programming inter- face when a special programming voltage is applied to ...
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C8051T620/621/320/321/322/323 18.1.2. EPROM In-Application Programming The EPROM of the C8051T620/621/320/321/322/323 devices has an In-Application Programming option. In-Application Programming will be much slower than normal programming where the V voltage is applied to the V pin, but it allows a small ...
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Security Options The C8051T620/621/320/321/322/323 devices provide security options to prevent unauthorized viewing of proprietary program code and constants. A security byte stored at location 0x3FF8 in the EPROM address space can be used to lock the program memory from ...
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C8051T620/621/320/321/322/323 example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. 18.3.2. PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set There ...
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SFR Definition 18.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F Bit Name 7:1 Unused Unused. Read = 0000000b. Write = don’t care. 0 PSWE Program Store Write Enable. ...
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C8051T620/621/320/321/322/323 SFR Definition 18.3. IAPCN: In-Application Programming Control Bit 7 6 IAPEN IAPDISD Name R/W R/W Type 0 0 Reset SFR Address = 0xF5 Bit Name 7 IAPEN In-Application Programming Enable. 0: In-Application Programming is disabled. 1: In-Application Programming is ...
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Power Management Modes The C8051T620/621/320/321/322/323 devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by ...
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C8051T620/621/320/321/322/323 vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi- nitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer Reset” on page 120 ...
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SFR Definition 19.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop Mode ...
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C8051T620/621/320/321/322/323 20. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to ...
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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...
Page 118
C8051T620/621/320/321/322/323 the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source. ...
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SFR Definition 20.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is ...
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C8051T620/621/320/321/322/323 20.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled ...
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SFR Definition 20.2. RSTSRC: Reset Source Bit 7 6 USBRSF MEMERR C0RSEF Name R/W R Type Varies Varies Varies Reset SFR Address = 0xEF Bit Name Description 7 USBRSF USB Reset Flag 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF ...
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C8051T620/621/320/321/322/323 21. Oscillators and Clock Selection C8051T620/621/320/321/322/323 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high- frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL ...
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System Clock Selection The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the exter- nal ...
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C8051T620/621/320/321/322/323 SFR Definition 21.1. CLKSEL: Clock Select Bit 7 6 USBCLK[2:0] Name R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7 Unused Unused. Read = 0b; Write = Don’t Care 6:4 USBCLK[2:0] USB Clock Source Select Bits. ...
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Programmable Internal High-Frequency (H-F) Oscillator All C8051T620/621/320/321/322/323 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR ...
Page 126
C8051T620/621/320/321/322/323 SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. ...
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Clock Multiplier The C8051T620/621/320/321/322/323 device includes a 48 MHz high-frequency oscillator instead MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high- frequency oscillator. For compatibility with ...
Page 128
C8051T620/621/320/321/322/323 21.5. Programmable Internal Low-Frequency (L-F) Oscillator All C8051T620/621/320/321/322/323 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the ...
Page 129
External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. Figure 21.1 shows a block diagram of the four external oscil- ...
Page 130
C8051T620/621/320/321/322/323 kHz 13 pF Figure 21.2. External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on ...
Page 131
External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, ...
Page 132
C8051T620/621/320/321/322/323 SFR Definition 21.6. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2:0] R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and is valid at all ...
Page 133
Port Input/Output Digital and analog resources are available through 21, 24 I/O pins, depending on the specific device. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or ...
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C8051T620/621/320/321/322/323 22.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all ...
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Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than V and less than 5.25V. An external pull-up resistor to the ...
Page 136
C8051T620/621/320/321/322/323 Table 22.2. Port I/O Assignment for Digital Functions Digital Function UART0, SPI0, SMBus, CP0, Any Port pin available for assignment by the CP0A, CP1, CP1A, Crossbar. This includes P0.0 - P2.6 pins which SYSCLK, PCA0 (CEX0-4 have their PnSKIP ...
Page 137
Table 22.3. Port I/O Assignment for External Digital Event Capture Functions Digital Function External Interrupt 0 External Interrupt 1 Port Match 22.3. Priority Crossbar Decoder The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top ...
Page 138
C8051T620/621/320/321/322/323 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1 RX1 ...
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C8051T620/621/320/321/322/323 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1 RX1 ...
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C8051T620/621/320/321/322/323 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1 RX1 ...
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... Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter- mine the Port I/O pin-assignments based on the XBRn Register settings. ...
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C8051T620/621/320/321/322/323 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name CP1AE CP1E Type R/W R/W Reset 0 0 SFR Address = 0xE1 Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 unavailable at Port ...
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SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE Type R/W R/W Reset 0 0 SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for ...
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C8051T620/621/320/321/322/323 SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xE3 Bit Name 7:1 Unused Unused. Read = 0000000b; Write = Don’t Care. 0 URT1E UART1 I/O ...
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SFR Definition 22.4. P0MASK: Port 0 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAE Bit Name 7:0 P0MASK[7:0] Port 0 Mask Value. Selects P0 pins to be compared to the corresponding bits in P0MAT. ...
Page 146
C8051T620/621/320/321/322/323 SFR Definition 22.6. P1MASK: Port 1 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xBA Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in ...
Page 147
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port cell can be configured for analog or digital I/O. This selection is required even for the digital resources selected in the ...
Page 148
C8051T620/621/320/321/322/323 SFR Definition 22.9. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak ...
Page 149
SFR Definition 22.11. P0SKIP: Port 0 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the ...
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C8051T620/621/320/321/322/323 SFR Definition 22.13. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 22.15. P1SKIP: Port 1 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the ...
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C8051T620/621/320/321/322/323 SFR Definition 22.17. P2MDIN: Port 2 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF3 Bit Name 7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 22.19. P2SKIP: Port 2 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD6 Bit Name 7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be skipped by the ...
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C8051T620/621/320/321/322/323 SFR Definition 22.21. P3MDOUT: Port 3 Output Mode Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xA7 Bit Name 7:1 Unused Unused. Read = 0000000b; Write = Don’t Care 0 P3MDOUT[0] Output Configuration Bits ...
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Universal Serial Bus Controller (USB0) C8051T620/621/320/321/322/323 devices include a complete Full/Low Speed USB function for USB peripheral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), ...
Page 156
C8051T620/621/320/321/322/323 Table 23.1. Endpoint Addressing Scheme Endpoint Associated Pipes Endpoint0 Endpoint1 Endpoint2 Endpoint3 Endpoint3 IN Endpoint3 OUT 23.2. USB Transceiver The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 23.1. This configu- ration includes Transceiver enable/disable, ...
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SFR Definition 23.1. USB0XCN: USB0 Transceiver Control Bit 7 6 PREN PHYEN SPEED Name R/W R/W Type 0 0 Reset SFR Address = 0xD7 Bit Name 7 PREN Internal Pull-up Resistor Enable. The location of the pull-up resistor (D+ or ...
Page 158
C8051T620/621/320/321/322/323 23.3. USB Register Access The USB0 controller registers listed in Table 23.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. ...
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SFR Definition 23.2. USB0ADR: USB0 Indirect Address Bit 7 6 BUSY AUTORD Name R/W R/W Type 0 0 Reset SFR Address = 0x96 Bit Name Description 7 BUSY USB0 Register Read Busy Flag. This bit is used during indirect USB0 ...
Page 160
C8051T620/621/320/321/322/323 SFR Definition 23.3. USB0DAT: USB0 Data Bit 7 6 Name Type 0 0 Reset SFR Address = 0x97 Bit Name Description 7:0 USB0DAT[7:0] USB0 Data Bits. This SFR is used to indi- rectly read and write USB0 registers. 160 ...
Page 161
Table 23.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F EENABLE 0x1E FIFOn 0x20-0x23 E0CSR ...
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C8051T620/621/320/321/322/323 USB Register Definition 23.4. INDEX: USB0 Endpoint Index Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x0E Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3:0 EPSEL[3:0] Endpoint Select ...
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USB Register Definition 23.5. CLKREC: Clock Recovery Control Bit 7 6 CRE CRSSEN CRLOW Name R/W R/W Type 0 0 Reset USB Register Address = 0x0F Bit Name 7 CRE Clock Recovery Enable Bit. This bit enables/disables the USB clock ...
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C8051T620/621/320/321/322/323 0x07FF Endpoint0 (64 bytes) 0x07C0 0x07BF Endpoint1 (128 bytes) 0x0740 0x073F Endpoint2 (256 bytes) 0x0640 0x063F Endpoint3 (512 bytes) 0x0440 0x043F Free (64 bytes) 0x0400 0x03FF User XRAM (1024 bytes) 0x0000 Figure 23.3. USB FIFO Allocation 23.5.1. FIFO Split ...
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Table 23.3. FIFO Configurations Endpoint Split Mode Number Enabled 23.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register ...
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C8051T620/621/320/321/322/323 23.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7- bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR ...
Page 167
See Section “21.3. Programmable Internal High-Frequency (H-F) Oscillator” on page 125 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits ...
Page 168
C8051T620/621/320/321/322/323 USB Register Definition 23.8. POWER: USB0 Power Bit 7 6 ISOUD Name R/W R/W Type 0 0 Reset USB Register Address = 0x01 Bit Name 7 ISOUD ISO Update Bit. This bit affects all IN Isochronous endpoints. 0: When ...
Page 169
USB Register Definition 23.9. FRAMEL: USB0 Frame Number Low Bit 7 6 Name Type 0 0 Reset USB Register Address = 0x0C Bit Name 7:0 FRMEL[7:0] Frame Number Low Bits. This register contains bits 7-0 of the last received frame ...
Page 170
C8051T620/621/320/321/322/323 USB Register Definition 23.11. IN1INT: USB0 IN Endpoint Interrupt Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x02 Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 IN3 IN ...
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USB Register Definition 23.12. OUT1INT: USB0 OUT Endpoint Interrupt Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x04 Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 OUT3 OUT Endpoint ...
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C8051T620/621/320/321/322/323 USB Register Definition 23.13. CMINT: USB0 Common Interrupt Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x06 Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 SOF Start of ...
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USB Register Definition 23.14. IN1IE: USB0 IN Endpoint Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x07 Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 IN3E IN ...
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C8051T620/621/320/321/322/323 USB Register Definition 23.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x09 Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 OUT3E ...
Page 175
USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x0B Bit Name 7:4 Unused Unused. Read = 0000b. Write = don’t care. 3 SOFE Start of ...
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C8051T620/621/320/321/322/323 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). The E0CNT register (USB Register Definition 23.11) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will ...
Page 177
Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware ...
Page 178
C8051T620/621/320/321/322/323 USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control Bit 7 6 SSUEND SOPRDY Name R/W R/W Type 0 0 Reset USB Register Address = 0x11 Bit Name Description 7 SSUEND Serviced Setup End Bit. 6 SOPRDY Serviced OPRDY Bit. ...
Page 179
USB Register Definition 23.18. E0CNT: USB0 Endpoint0 Data Count Bit 7 6 Name R Type 0 0 Reset USB Register Address = 0x16 Bit Name 7 Unused Unused. Read = 0b. Write = don’t care. 6:0 E0CNT[6:0] Endpoint 0 Data ...
Page 180
C8051T620/621/320/321/322/323 USB Register Definition 23.19. EENABLE: USB0 Endpoint Enable Bit 7 6 Name R R Type 1 1 Reset USB Register Address = 0x1E Bit Name 7:4 Unused Unused. Read = 1111b. Write = don’t care. 3 EEN3 Endpoint 3 ...
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A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener- ates a ...
Page 182
C8051T620/621/320/321/322/323 USB Register Definition 23.20. EINCSRL: USB0 IN Endpoint Control Low Bit 7 6 CLRDT Name R W Type 0 0 Reset USB Register Address = 0x11 Bit Name Description 7 Unused Unused. Read = 0b. Write = don’t care. ...
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USB Register Definition 23.21. EINCSRH: USB0 IN Endpoint Control High Bit 7 6 DBIEN ISO DIRSEL Name R/W R/W Type 0 0 Reset USB Register Address = 0x12 Bit Name 7 DBIEN IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for ...
Page 184
C8051T620/621/320/321/322/323 23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH. the target endpoint operates in Bulk or Interrupt mode. Once an end- point has been configured to operate in Bulk/Interrupt OUT mode (typically following an ...
Page 185
USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Bit 7 6 CLRDT STSTL SDSTL Name W R/W Type 0 0 Reset USB Register Address = 0x14 Bit Name Description 7 CLRDT Clear Data Toggle Bit. Software should ...
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C8051T620/621/320/321/322/323 USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte Bit 7 6 DBOEN ISO Name R/W R/W Type 0 0 Reset USB Register Address = 0x15 Bit Name 7 DBOEN Double-buffer Enable. 0: Double-buffering disabled for the ...
Page 187
USB Register Definition 23.25. EOUTCNTH: USB0 OUT Endpoint Count High Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x17 Bit Name 7:2 Unused Unused. Read = 000000b. Write = don’t care. 1:0 EOCH[1:0] OUT ...
Page 188
C8051T620/621/320/321/322/323 24. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with ...
Page 189
Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, ...
Page 190
C8051T620/621/320/321/322/323 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE ...
Page 191
SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 24.3.5. SCL High (SMBus Free) Timeout The SMBus specification ...
Page 192
C8051T620/621/320/321/322/323 Table 24.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as ...
Page 193
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines ...
Page 194
C8051T620/621/320/321/322/323 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...
Page 195
SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 24.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
Page 196
C8051T620/621/320/321/322/323 SFR Definition 24.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is ...
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Table 24.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed by ...
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C8051T620/621/320/321/322/323 In this case, either value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 24.4 ...
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SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask Bit 7 6 Name Type 1 1 Reset SFR Address = 0xCF Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address ...
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C8051T620/621/320/321/322/323 24.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...