M95256-WMN6P STMicroelectronics, M95256-WMN6P Datasheet - Page 24

• Manufacturer Part Number: M95256-WMN6P
• Description: IC EEPROM 256KBIT 5MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95256-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 32 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 60 ns
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 130 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 32K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6357-5; M95256-WMN6P

Instructions
5.8
24/48
Write Identification Page (available only in M95256-DR
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see
Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at
least one data byte are then shifted in on Serial Data input (D). Address bit A10 must be 0,
address bits [A23:A11] and [A9:A8] are Don't Care, the [A7:A0] address bits define the byte
address inside the identification page. The instruction is terminated by driving Chip Select
(S) high at a byte boundary of the input data. The self-timed write cycle triggered by the
rising edge of Chip Select (S) continues for a period t
of which the Write in Progress (WIP) bit is reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle. Each time
a new data byte is shifted in, the least significant bits of the internal address counter are
incremented. If the number of data bytes sent to the device exceeds the page boundary, the
internal address counter rolls over to the beginning of the page, and the previous data there
are overwritten with the incoming data. (The page size of these devices is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
●
Figure 14. Write Identification Page sequence
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
if Status register bits (BP1, BP0) = (1, 1)
if a write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
if the Identification page is locked by the Lock Status bit
Figure
14, Chip Select (S) is driven high after the eighth bit of the data byte
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
W
(as specified in
Figure
Table
14, the next byte
20), at the end
Table
4), the