IDT71V3576S133PF IDT, Integrated Device Technology Inc, IDT71V3576S133PF Datasheet - Page 2

• Manufacturer Part Number: IDT71V3576S133PF
• Description: IC SRAM 4MBIT 133MHZ 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71V3576S133PF

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 71V3576S133PF

Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
I/O
BW
I/O
Symbol
A
ADSC
ADSP
TRST
BWE
V
ADV
P1
TMS
LBO
TCK
TDO
CLK
CS
GW
V
V
0
CS
OE
CE
0
TDI
1
ZZ
NC
DDQ
-A
-I/O
DD
SS
-BW
-I/O
0
1
17
31
P4
4
Linear Burst Order
(Cache Controller)
Byte Write Enable
Test ModeSelect
Data Input/Output
Test DataOutput
Address Inputs
Address Status
Address Status
Test Data Input
Individual Byte
Burst Address
Write Enables
Output Enable
Power Supply
Power Supply
Chip Select 0
Pin Function
Chip Select 1
Chip Enable
Global Write
Sleep Mode
JTAG Reset
No Connect
(Processor)
Test Clock
(Optional)
Advance
Ground
Enable
Clock
(1)
N/A
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge
of CLK and ADSC Low or ADSP Low and CE Low.
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst
counter is not incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW
edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the
byte write inputs are blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW
byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must
not change state while the device is operating.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has
an internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
Serial output of registers placed between TDI and TDO. This output is active depending on the state
of the TAP controller.
Optional Asynchrono us JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep
Mode.This pin has an internal pull down.
Ground.
NC pins are not electrically connected to the device.
the address registers with new addresses.
ADSP.
This is the clock input. All timing references for the device are made with respect to this input.
Async hronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if
the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
3.3V core power supply.
3.3V I/O Supply.
6.42
2
1
controls I/O
Commercial and Industrial Temperature Ranges
1
0
is used with CE and CS
is used with CE and CS
0
and CS
0-7
, I/O
1
P1
to enable the IDT71V3576/78. CE also gates
, BW
1
-BW
2
controls I/O
0
4
1
. If BWE is LOW at the rising
to enable the chip.
to enable the chip.
8-15
, I/O
P2
, etc. Any active
5279 tbl 02