IDT71V3576S133PF IDT, Integrated Device Technology Inc, IDT71V3576S133PF Datasheet

no-image

IDT71V3576S133PF

Manufacturer Part Number
IDT71V3576S133PF
Description
IC SRAM 4MBIT 133MHZ 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71V3576S133PF

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71V3576S133PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71V3576S133PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3576S133PF
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT71V3576S133PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3576S133PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3576S133PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3576S133PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Features
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
NOTE:
1. BW
Pin Description Summary
©2004 Integrated Device Technology, Inc.
CS
CLK
I/O
A
CE
OE
GW
BWE
BW
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
V
V
0
DD
SS
-A
0
0
128K x 36, 256K x 18 memory configurations
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
1
-I/O
, CS
, V
, BW
17
DDQ
3
31
1
, I/O
and BW
2
, BW
P1
3
-I/O
, BW
4
P4
are not applicable for the IDT71V3578.
4
(1)
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
1
Description
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
The IDT71V3576/78 are high-speed SRAMs organized as
The burst mode feature offers the highest level of performance to the
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance
Supply
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
FEBRUARY 2009
IDT71V3576SA
IDT71V3578SA
IDT71V3576S
IDT71V3578S
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
N/A
N/A
N/A
N/A
DC
DSC-5279/04
5279 tbl 01

Related parts for IDT71V3576S133PF

IDT71V3576S133PF Summary of contents

Page 1

... Features ◆ ◆ ◆ ◆ ◆ 128K x 36, 256K x 18 memory configurations ◆ ◆ ◆ ◆ ◆ Supports high system speed: Commercial and Industrial: – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode ◆ ...

Page 2

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Definitions (1) Symbol Pin Function I Address Inputs Address Status ADSC I (Cache ...

Page 3

... Byte 4 Write Register Q D Enable Register CLK Enable Delay Register TDO 6.42 3 INTERNAL ADDRESS 128K x 36/ 17/18 256K x 18- A0* BIT MEMORY A1* ARRAY 17 36/18 36/18 Byte 1 Write Driver 9 Byte 2 Write Driver 9 Byte 3 Write Driver 9 Byte 4 Write Driver 9 OUTPUT REGISTER DATA INPUT REGISTER ...

Page 4

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with ...

Page 5

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 I/O 1 ...

Page 6

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 256K DDQ ...

Page 7

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 119 BGA DDQ I ...

Page 8

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 165 fBGA ( ...

Page 9

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ...

Page 10

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power ...

Page 11

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H ...

Page 12

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time ...

Page 13

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 13 ...

Page 14

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges , 6.42 14 (1,2,3) ...

Page 15

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 16

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 17

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 18

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA ...

Page 19

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / ...

Page 20

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID ...

Page 21

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Ordering Information XXX Device Power Speed Package Type Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) ...

Page 22

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Datasheet Document History 7/26/99 9/17/99 Pg. 8 Pg. 11 Pg. 18 Pg. 20 12/31/99 Pg 11, 19 ...

Related keywords