CY7C1354CV25-166AXC Cypress Semiconductor Corp, CY7C1354CV25-166AXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1354CV25-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1354CV25-166AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 2.625 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2121; CY7C1354CV25-166AXC

Truth Table
Document Number: 38-05537 Rev. *K
NOP/WRITE ABORT (begin burst)
WRITE ABORT (continue burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Read
Write – no bytes written
Write byte a– (DQ
Write byte b – (DQ
Write bytes b, a
Write byte c – (DQ
Write bytes c, a
Write bytes c, b
Write bytes c, b, a
Write byte d – (DQ
Write bytes d, a
Write bytes d, b
Write bytes d, b, a
Write bytes d, c
Write bytes d, c, a
Write bytes d, c, b
Write all bytes
Read
Write – no bytes written
Write byte a − (DQ
Write byte b – (DQ
Write both bytes
Note
Partial Write Cycle Description
Partial Write Cycle Description
9. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid
10. Write is defined by WE and BW
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any combination of BW
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
Operation
Function (CY7C1354CV25)
[2, 3, 4, 5, 6, 7, 8]
a
c
b
d
a
b
and DQP
and DQP
and DQP
and DQP
and DQP
Function (CY7C1356CV25)
and DQP
X
a
. See Write Cycle Description table for details.
c
b
a
d
b
)
)
)
)
)
)
Address used CE ZZ
Current
None
None
Next
[9, 10, 11, 12]
[9, 10, 11, 12]
X
X
X
L
H
L
L
L
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
X
L
X
X
is valid. Appropriate write will be done based on which byte write is active.
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
WE
L
X
X
X
d
WE
H
L
L
L
L
BWx
H
H
X
X
BW
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
OE
X
X
X
X
c
BW
CEN
H
H
x
L
L
H
X
L
L
b
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
CY7C1354CV25
CY7C1356CV25
CLK
L-H
L-H
L-H
X
b
Tri-state
Tri-state
Tri-state
BW
DQ
H
H
x
L
L
Page 10 of 30
–
BW
a
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
a
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