CY7C1354CV25-166AXC Cypress Semiconductor Corp, CY7C1354CV25-166AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C1354CV25-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1354CV25-166AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 2.625 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2121; CY7C1354CV25-166AXC

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package only.
The TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V I/O logic levels.
The
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
internally pulled up and may be unconnected. They may
alternately be connected to V
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
TAP Controller State Diagram
Document Number: 38-05537 Rev. *K
Note
13. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
SS
1
0
) to prevent clocking of the device. TDI and TMS are
TEST-LOGIC
CY7C1354CV25/CY7C1356CV25
RUN-TEST/
RESET
IDLE
0
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
DD
0
0
1
0
1
1
0
through a pull-up resistor. TDO
1
1
0
0
[13]
contains
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
EXIT1-IR
EXIT2-IR
1
IR-SCAN
SHIFT-IR
SELECT
0
0
1
0
1
1
0
a
1
1
0
0
TAP
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used.
The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see
Diagram
if the TAP is unused in an application. TDI is connected to the
most significant bit (MSB) of any register. (See
Block
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See
Diagram).
[13]
. TDI is internally pulled up and can be unconnected
TAP Controller State Diagram
CY7C1354CV25
CY7C1356CV25
TAP Controller State
[13]
).
TAP Controller
Page 11 of 30
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