CY7C1354CV25-166AXC Cypress Semiconductor Corp, CY7C1354CV25-166AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1354CV25-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1354CV25-166AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 2.625 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2121; CY7C1354CV25-166AXC

table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1354CV25 and CY7C1356CV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
CY7C1356CV25) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ and DQP (DQ
CY7C1354CV25 and DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1354CV25/CY7C1356CV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in the
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
(BW
inputs must be driven in each cycle of the burst write in order to
write the correct bytes of data.
ZZ Mode Electrical Characteristics
Truth Table
Document Number: 38-05537 Rev. *K
I
t
t
t
t
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
Notes
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = Valid
3. Write is defined by WE and BW
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
is inactive or when the device is deselected, and DQs = data when OE is active.
a,b,c,d
a,b,c,d
Parameter
remain
/DQP
for CY7C1354CV25 and BW
Operation
unaltered.
a,b,c,d
[2, 3, 4, 5, 6, 7, 8]
for CY7C1354CV25 and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b
1
A
, CE
X
/DQP
. See Write Cycle Description table for details.
synchronous
2
, and CE
Single Write Accesses
Description
a,b
Address used CE ZZ
for CY7C1356CV25) are
a,b
External
External
External
None
None
Next
Next
Next
3
for CY7C1356CV25)
) and WE inputs are
a,b,c,d
self-timed
/DQP
a,b
/DQP
H
X
X
X
X
L
L
L
a,b,c,d
section
a,b
L
L
L
L
L
L
L
L
write
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
for
for
ADV/LD
DD
DD
H
H
H
H
L
L
L
L
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
− 0.2 V
Test Conditions
− 0.2 V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
00
01
10
11
11
3,
WE
H
H
X
X
X
X
L
X
must remain inactive for the duration of t
BWx
X
X
X
X
X
X
L
L
Address
Address
Second
Second
A1, A0
A1, A0
01
10
11
00
01
00
10
11
OE
H
H
X
X
L
L
X
X
CEN
2t
L
L
L
L
L
L
L
L
DD
Min
CYC
–
–
–
0
Address
Address
A1, A0
A1, A0
)
Third
Third
CY7C1354CV25
CY7C1356CV25
10
00
01
CLK
11
10
11
00
01
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
2t
2t
= tri-state when OE
Max
50
CYC
CYC
–
–
Data out (Q)
Data out (Q)
Data in (D)
Data in (D)
Tri-state
Tri-state
Tri-state
Tri-state
DQ
ZZREC
Address
Address
Fourth
Fourth
A1, A0
A1, A0
Page 9 of 30
Unit
10
01
00
11
00
01
10
11
mA
ns
ns
ns
ns
after the
1
, CE
2
[+] Feedback
,