CY7C1250V18-333BZC Cypress Semiconductor Corp, CY7C1250V18-333BZC Datasheet

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... K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, which share the same ...

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... Logic Block Diagram (CY7C1248V18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1250V18 (18:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06348 Rev. *E Write Write Reg ...

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... DQ35 DQ25 DQ26 R TDO TCK A Document Number: 001-06348 Rev. *E CY7C1248V18 ( NC/144M R/W BWS NC/288M K BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD CY7C1250V18 ( R/W BWS K BWS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD CY7C1248V18 CY7C1250V18 ...

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... Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each 18) for CY7C1248V18, and arrays each of 512K x 36) for CY7C1250V18. R/W Input- Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address ...

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... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and REF Reference AC measurement points. V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06348 Rev. *E CY7C1248V18 CY7C1250V18 Pin Description Page [+] Feedback ...

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... Functional Overview The CY7C1248V18, and CY7C1250V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the rising edge of the input clocks (K and K). All synchronous data inputs (D ...

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... Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Truth Table The truth table for the CY7C1248V18, and CY7C1250V18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) Load address ...

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... D remains unaltered. [8:0] [17: written into the device, D remains unaltered. [17:9] [8: written into the device, D remains unaltered. [17:9] [8:0] table. BWS , BWS , BWS , and BWS can be altered on different portions of a write cycle CY7C1248V18 CY7C1250V18 Page [+] Feedback ...

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... Write Cycle Descriptions The write cycle descriptions table for CY7C1250V18 follows. BWS BWS BWS BWS L – L – L – L – L – L – Document Number: 001-06348 Rev Comments – During the data portion of a write sequence, all four bytes (D into the device. L-H During the data portion of a write sequence, all four bytes (D into the device. – ...

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... TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. CY7C1248V18 CY7C1250V18 “TAP Controller Block Diagram” when the BYPASS SS shows the order in which the “ ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06348 Rev. *E CY7C1248V18 CY7C1250V18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06348 Rev. *E [9] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1248V18 CY7C1250V18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...

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... Boundary Scan Register TAP Controller Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ − /2). Undershoot: V (AC) > 0.3V (pulse width less than t CYC IL CY7C1248V18 CY7C1250V18 Selection Circuitry TDO Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD −5 μ ...

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... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-06348 Rev. *E Description [14] Figure 2. TAP Timing and Test Conditions 50Ω 1. TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1248V18 CY7C1250V18 Min Max Unit MHz ALL INPUT PULSES 0.9V t TCYC t ...

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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1248V18 CY7C1250V18 Description 000 Version number. Defines the type of SRAM. ...

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... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1248V18 CY7C1250V18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...

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... DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. REF Figure 3. Power Up Waveforms > 2048 Stable Clock DDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to V DDQ ) CY7C1248V18 CY7C1250V18 . KC Var Start Normal Operation Page [+] Feedback ...

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... MHz 375 MHz (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175Ω < RQ < 350Ω. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1248V18 CY7C1250V18 Test Con- Description Typ Max* ditions Logical 25°C 320 368 Single-Bit Upsets Logical 25° ...

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... V 0.75V R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1248V18 CY7C1250V18 Min Typ Max Unit 290 300 320 Min Typ. Max Unit V + 0.2 – 0.24 REF DDQ –0.24 – V – 0.2 ...

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... V - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t KHKH “AC Test Loads and Waveforms” on page and t less than t . CLZ CHZ CO CY7C1248V18 CY7C1250V18 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max 1 – 1 – 1 – ...

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... Figure 5. Waveform for 2.0 Cycle Read Latency NOP NOP NOP WRITE QVLD Q00 Q01 Q10 Q11 t t DOH CHZ CQD t CQDOH t CCQO t CCQO CY7C1248V18 CY7C1250V18 WRITE READ NOP NOP QVLD D20 D21 Q40 Q41 D30 D31 t t CQH CQHCQH DON’T CARE UNDEFINED Page [+] Feedback ...

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... Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office http://www.cypress.com/go/datasheet/offices closest to you, visit us at Table 1. Ordering Information Speed (MHz) Ordering Code 333 CY7C1250V18-333BZC CY7C1250V18-333BZXC CY7C1250V18-333BZI Package Diagram Figure 6. 165-Ball FBGA ( 1.40 mm), 51-85195 Document Number: 001-06348 Rev. *E www.cypress.com Package ...

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... Document History Page Document Title: CY7C1248V18/CY7C1250V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-06348 Submission REV. ECN No. Date ** 425689 See ECN *A 461639 See ECN *B 497628 See ECN *C 1093183 See ECN *D 2198506 See ECN *E 2755831 08/25/2009 Document Number: 001-06348 Rev. *E Orig ...

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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06348 Rev. *E All product and company names mentioned in this document are the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised August 24, 2009 CY7C1248V18 CY7C1250V18 Page [+] Feedback ...