CY7C1250V18-333BZC Cypress Semiconductor Corp, CY7C1250V18-333BZC Datasheet - Page 17

• Manufacturer Part Number: CY7C1250V18-333BZC
• Description: IC SRAM 36MBIT 333MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1250V18-333BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 333MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS compliant by exemption

Power Up Sequence in DDR II+ SRAM
DDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
Power Up Sequence
■
■
Document Number: 001-06348 Rev. *E
Apply power with DOFF tied HIGH (all other inputs can be HIGH
or LOW)
❐
❐
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
Apply V
Apply V
V DD /V DDQ
DOFF
DD
DDQ
before V
before V
K
K
DDQ
REF
or at the same time as V
Clock Start (Clock Starts after V DD /V DDQ is Stable)
Unstable Clock
V DD /V DDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to V DDQ )
Figure 3. Power Up Waveforms
REF
> 2048 Stable Clock
DLL Constraints
■
■
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Start Normal
Operation
CY7C1248V18
CY7C1250V18
KC Var
Page 17 of 24
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