HYB25D512800CE-6 Qimonda, HYB25D512800CE-6 Datasheet - Page 3

• Manufacturer Part Number: HYB25D512800CE-6
• Description: IC DDR SDRAM 512MBIT 66TSOP
• Manufacturer: Qimonda

Specifications of HYB25D512800CE-6

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1008-2

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Programmable CAS latency: 2, 2.5, 3
• Programmable burst lengths: 2, 4, or 8
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported
• 7.8 μs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
•
•
• Packages: PG-TSOPII-66, PG-TFBGA-60, P-TSOPII-66, P-TFBGA-60
• RoHS Compliant Products
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
Part Number Speed Code
Speed Grade
Max. Clock Frequency
V
V
DD
DDQ
= 2.5 V ± 0.2 V
= 2.5 V ± 0.2 V
Overview
Features
t
RAP
=
t
RCD
Component
@CL3
@CL2.5
@CL2
Date: 2007-12-13
f
f
f
CK3
CK2.5
CK2
3
–5
DDR400B
200
166
133
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
–6
DDR333B
166
166
133
Internet Data Sheet
Performance
TABLE 1
Unit
—
MHz
MHz
MHz