HYB25D512800CE-6 Qimonda, HYB25D512800CE-6 Datasheet - Page 30

• Manufacturer Part Number: HYB25D512800CE-6
• Description: IC DDR SDRAM 512MBIT 66TSOP
• Manufacturer: Qimonda

Specifications of HYB25D512800CE-6

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1008-2

1) 0 °C ≤ T
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until
4)
5) The value of
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
Parameter
DQ output access time from
CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
DQ and DM input hold time
DQ and DM input pulse width
(each input)
DQS output access time from
CK/CK
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1
latching transition
DQ and DM input setup time
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
A
≤ 70 °C;
V
IX
is expected to equal 0.5 ×
V
st
DD
DQS
=
V
DDQ
= 2.5 V ± 0.2 V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CH
CK
CL
DAL
DH
DIPW
DQSCK
DQSL,H
DQSQ
DQSQ
DQSS
DS
V
REF
V
stabilizes.
DDQ
of the transmitting device and must track variations in the DC level of the same.
–5
–0.7
0.45
5
6
7
0.45
Min. : (
0.4
1.75
–0.6
0.35
—
—
0.72
0.4
DDR400
Min.
Date: 2007-12-13
t
WR
/
t
Symbol
V
V
V
V
CK
IH.AC
IL.AC
ID.AC
IX.AC
30
)+(
Max.
+0.7
0.55
8
12
12
0.55
—
—
+0.6
—
+0.40
+0.40
1.25
—
t
RP
/
t
CK
Min.
V
—
0.7
0.5 ×
), Max. : —
REF
–6
DDR333
Min.
–0.7
0.45
6
6
7.5
0.45
0.45
1.75
–0.6
0.35
—
—
0.75
0.45
+ 0.31
V
DDQ
– 0.2 0.5 ×
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
AC Timing - Absolute Specifications
Values
512-Mbit Double-Data-Rate SDRAM
Max.
+0.7
0.55
12
12
12
0.55
—
—
+0.6
—
+0.45
+0.40
1.25
—
Max.
—
V
V
REF
DDQ
– 0.31
+ 0.6
V
AC Operating Conditions
DDQ
Unit
ns
t
ns
ns
ns
t
t
ns
ns
ns
t
ns
ns
t
ns
CK
CK
CK
CK
CK
+ 0.2
Internet Data Sheet
Unit Note/ Test
V
V
V
V
Note/ Test
Condition
2)3)4)5)
2)3)4)5)
CL = 3.0
CL = 2.5
CL = 2.0
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
TSOPII
TFBGA
2)3)4)5)
2)3)4)5)
TABLE 22
TABLE 23
Condition
1)2)3)
1)2)3)
1)2)3)4)
1)2)3)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
1)