CY7C1321CV18-167BZC Cypress Semiconductor Corp, CY7C1321CV18-167BZC Datasheet

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... CY7C1319CV18, and four 36-bit words in the case of CY7C1321CV18, sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same ...

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... Logic Block Diagram (CY7C1917CV18 (18:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Write Write Write Write Reg Reg Reg Reg Output Logic Control Read Data Reg Reg. Reg. 16 Reg. Write Write ...

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... Logic Block Diagram (CY7C1319CV18) Burst A (1:0) Logic (19:0) A Address (19:2) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1321CV18) Burst A (1:0) Logic (18:0) A Address (18:2) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-07161 Rev ...

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... Pin Configuration The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow NC/72M DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK NC/72M DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow NC/72M DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M NC/36M B NC DQ27 DQ18 DQ28 D NC DQ29 DQ19 E NC ...

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... CY7C1319CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array. CY7C1321CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array. ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Description Switching Characteristics on page 24. Switching Characteristics on page 24. output impedance are set to 0.2 x RQ, where resistor connected [x:0] ...

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... Functional Overview The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V behaves in DDR-I mode with a read latency of one clock cycle. ...

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... Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Echo Clocks Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II ...

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... Device powers up deselected with the outputs in a tri-state condition CY7C1319CV18 and CY7C1321CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2”, “A3”, “A4” represents the addresses sequence in the burst. On CY7C1317CV18 and CY7C1917CV18, “A1” represents A + ‘00’ and “A2” represents A + ‘01’, “A3” represents A + ‘10’ and “A4” ...

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... No data is written into the device during this portion of a write operation. Note 8. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Third Address (Internal) X..X01 X..X10 X..X10 X..X11 X ...

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... Write Cycle Descriptions The write cycle description table for CY7C1321CV18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 [ Comments – During the Data portion of a write sequence, all four bytes (D the device. L– ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 0 Bypass Register Instruction Register ...

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... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Value CY7C1917CV18 CY7C1319CV18 001 001 11010100011001101 11010100011010101 ...

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... Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 1H 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...

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... RQ < 350Ω. OL DDQ 18. V (min) = 0.68V or 0.46V , whichever is larger, V REF DDQ Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA Operating Range Range Commercial DD Industrial + 0.3V DDQ + 0 ...

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... DD I Automatic Power down SB1 Current AC Electrical Characteristics [11] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Test Conditions V = Max, 200MHz (x8 mA, OUT (x9 1/t MAX CYC (x18) (x36) 167MHz ...

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... RQ = 250Ω (a) Note 19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Test Conditions T = 25° MHz 1.8V DDQ Test Conditions ...

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... This part has an internal voltage regulator; t POWER 22. For DQ2 data signal on CY7C1917CV18 device, t Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [21] 1 – ...

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... CHZ CLZ 25. At any voltage and temperature t is less than t CHZ Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 28. In this example, if address A4 = A3, then data Q40 = D30, Q41 = D31, Q42 = D32, and Q43 = D43. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 [26, 27, 28] WRITE NOP NOP ...

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... CY7C1317CV18-278BZXI CY7C1917CV18-278BZXI CY7C1319CV18-278BZXI CY7C1321CV18-278BZXI Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... CY7C1317CV18-200BZXI CY7C1917CV18-200BZXI CY7C1319CV18-200BZXI CY7C1321CV18-200BZXI Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 167 CY7C1317CV18-167BZC CY7C1917CV18-167BZC CY7C1319CV18-167BZC CY7C1321CV18-167BZC CY7C1317CV18-167BZXC CY7C1917CV18-167BZXC CY7C1319CV18-167BZXC CY7C1321CV18-167BZXC CY7C1317CV18-167BZI CY7C1917CV18-167BZI CY7C1319CV18-167BZI CY7C1321CV18-167BZI CY7C1317CV18-167BZXI CY7C1917CV18-167BZXI ...

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... Package Diagram Figure 4. 165-ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-07161 Rev. *B CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... Document History Page Document Title: CY7C1317CV18/CY7C1917CV18/CY7C1319CV18/CY7C1321CV18, 18-Mbit DDR-II SRAM 4-Word Burst Architecture Document Number: 001-07161 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 433284 See ECN NXR *A 462615 See ECN NXR *B 1523383 See ECN VKN/AESA © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...