CY7C1321CV18-167BZC Cypress Semiconductor Corp, CY7C1321CV18-167BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1321CV18-167BZC
• Description: IC SRAM 18MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1321CV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.
Document Number: 001-07161 Rev. *B
SS
to enable the SRAM to adjust its output
,
with V
DDQ
= 1.5V. The
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR-II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in
Characteristics
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR-I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII™/DDRII.
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
on page 24.
Page 9 of 31
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