UPMU-M3L1X-B-EK Silicon Labs, UPMU-M3L1X-B-EK Datasheet - Page 51

• Manufacturer Part Number: UPMU-M3L1X-B-EK
• Description: Daughter Cards & OEM Boards UDP SiM3L1xx MCU Card (no LCD)
• Manufacturer: Silicon Labs

Specifications of UPMU-M3L1X-B-EK

• Product: MCU Cards
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Description/function: MCU Card (No LCD) to use with UDP Motherboard
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Tool Is For Evaluation Of: SiM3L1xx
• For Use With: SiM3L1xx

4.10. Security
The peripherals on the SiM3L1xx devices have a register lock and key mechanism that prevents undesired
accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A
key sequence must be written to the KEY register to modify bits in PERIPHLOCKx. Any subsequent write to KEY
will then inhibit accesses of PERIPHLOCKx until it is unlocked again through KEY. Reading the KEY register
indicates the current status of the PERIPHLOCKx lock state.
If a peripheral’s registers are locked, all writes will be ignored. The registers can be read, regardless of the
peripheral’s lock state.
4.11. On-Chip Debugging
The SiM3L1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for
instruction trace. The JTAG interface is supported on SiM3L1x7 devices only, and does not include boundary scan
capabilites. The ETM interface is supported on SiM3L1x7, and SiM3L1x6 devices only. The JTAG and ETM
interfaces can be optionally enabled to provide more visibility while debugging at the cost of using several Port I/O
pins. Additionally, if the core is configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer
(SWV) is available to provide a single pin to send out TPIU messages. Serial Wire Viewer is supported on all
SiM3Lxxx devices.
Most peripherals on SiM3L1xx devices have the option to halt or continue functioning when the core halts in debug
mode.
KEY
Figure 4.5. SiM3L1xx Security Block Diagram
Peripheral Lock and Key
PERIPHLOCK0
PERIPHLOCK1
Rev 0.5
SARADC0
TIMER0/1
USART0,
CMP0/1
UART0
EPCA0
SPI0/1
I2C0
SiM3L1xx
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