AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 16

• Manufacturer Part Number: AT25DF641-S3H-T
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.
16
Figure 7-5.
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip
Erase command can be started, the Write Enable command must have been previously issued to the device to
set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device
functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one
of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased,
no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the
internally self-timed and should take place in a time of t
The complete opcode must be clocked into the device before the
deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition,
if any sector of the memory array is in the protected or locked down state, then the Chip Erase command will not
be executed, and the device will return to the idle state once the
Status Register will be reset back to the logical “0” state if the
if a sector is in the protected or locked down state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
t
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Atmel AT25DF641
CHPE
SCK
SO
CS
SI
time to determine if the device has finished erasing. At some point before the erase cycle completes, the
CS
Block Erase
pin is deasserted, the device will erase the entire memory array. The erasing of the device is
MS B
HIG H-IMP E DANC E
C
0
C
1
C
2
OP C ODE
C
3
C
4
C
5
C
6
C
7
MS B
A
8
A
9
A
10 11
A
ADDR E S S B IT S A23-A0
A
12
A
CHPE
.
A
26
CS
A
27 28
CS
A
pin is deasserted on uneven byte boundaries or
CS
A
29 30
pin has been deasserted. The WEL bit in the
A
pin is deasserted, and the
A
31
CS
3680F–DFLASH–4/10
pin must be