AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 7

• Manufacturer Part Number: AT25DF641-S3H-T
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.
5.
3680F–DFLASH–4/10
Device Operation
The Atmel
referred to as the SPI Master. The SPI Master communicates with the AT25DF641 via the SPI bus which is
comprised of four signal lines: Chip Select (
The AT25DF641 features a dual-input program mode in which the SO pin become an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page
Program command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-
Output Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus.
The AT25DF641 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI
Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby
mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of
SCK and always output on the falling edge of SCK.
Figure 4-1.
Commands and Addressing
A valid instruction or operation must always be started by first asserting the
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode,
instruction dependent information such as address and data bytes would then be clocked out by the host
controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An
operation is ended by deasserting the
Opcodes not supported by the AT25DF641 will be ignored by the device and no operation will be started. The
device will continue to ignore any data presented on the SI pin until the start of the next operation (
deasserted and then reasserted). In addition, if the
information is sent to the device, then no operation will be performed and the device will simply return to the idle
state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-
A0. Since the upper address limit of the AT25DF641 memory array is 7FFFFFh, address bit A23 is always
ignored by the device.
SCK
SO
CS
SI
®
AT25DF641 is controlled by a set of instructions that are sent from a host controller, commonly
SPI Mode 0 and 3
MS B
CS
pin.
CS
), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
CS
LS B
pin is deasserted before complete opcode and address
MS B
CS
Atmel AT25DF641
pin. After the
LS B
CS
pin has been
CS
pin being
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