AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 45

IC FLASH 64MBIT 100MHZ 16SOIC

AT25DF641-S3H-T

Manufacturer Part Number
AT25DF641-S3H-T
Description
IC FLASH 64MBIT 100MHZ 16SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT25DF641-S3H-T

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
64M (32K pages x 256 bytes)
Speed
100MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25DF641-S3H-T
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT25DF641-S3H-T
Quantity:
730
11.5.
3680F–DFLASH–4/10
Hold
The
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a
program or erase cycle. Therefore, if an erase cycle is in progress, asserting the
operation, and the erase cycle will continue until it is finished.
The Hold mode can only be entered while the
the
mode won’t be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as
long as the
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored. The
To end the Hold mode and resume serial communication, the
pulse. If the
of the next SCK low pulse.
If the
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 11-5. Hold Mode
HOLD
SCK
CS
HOLD
HOLD
CS
pin is deasserted while the
pin during the SCK low pulse. If the
pin is used to pause the serial communication with the device without having to stop or reset the clock
HOLD
HOLD
pin and
pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning
WP
pin, however, can still be asserted or deasserted while in the Hold mode.
CS
pin are asserted.
HOLD
Hold
pin is still asserted, then any operation that may have been started will
CS
HOLD
pin is asserted. The Hold mode is activated simply by asserting
pin is asserted during the SCK high pulse, then the Hold
HOLD
Hold
pin must be deasserted during the SCK low
Atmel AT25DF641
HOLD
Hold
pin will not pause the
45

Related parts for AT25DF641-S3H-T