AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 21

IC FLASH 64MBIT 100MHZ 16SOIC

AT25DF641-S3H-T

Manufacturer Part Number
AT25DF641-S3H-T
Description
IC FLASH 64MBIT 100MHZ 16SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT25DF641-S3H-T

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
64M (32K pages x 256 bytes)
Speed
100MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25DF641-S3H-T
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT25DF641-S3H-T
Quantity:
730
8.
8.1.
3680F–DFLASH–4/10
Figure 7-8.
Protection Commands and Features
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1”
state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command
can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances
of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to
the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the
complete opcode must be clocked into the device before the
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and
the state of the WEL bit will not change.
Figure 8-1.
SCK
SCK
SO
SO
CS
CS
SI
SI
Program/Erase Resume
Write Enable
HIG H-IMP E DANC E
MS B
HIG H-IMP E DANC E
MS B
0
1
0
0
0
1
1
1
0
0
CS
2
2
OP C ODE
OP C ODE
0
1
3
3
pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The
0
0
4
4
0
1
5
5
0
1
6
6
0
0
7
7
CS
pin must first be asserted and the opcode of 06h must be clocked
CS
pin is deasserted, and the
Atmel AT25DF641
CS
pin must be
21

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