MA240026 Microchip Technology, MA240026 Datasheet - Page 168

• Manufacturer Part Number: MA240026
• Description: Daughter Cards & OEM Boards PIC24FJ16MC102 Plug-In Module
• Manufacturer: Microchip Technology

Specifications of MA240026

• Rohs: yes
• Data Bus Width: 16 bit
• Description/function: PIC24F 28 Pin QFN to 100 Pin Plug-in-Module
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V

PIC24FJ16MC101/102
REGISTER 18-1:
DS39997B-page 168
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
Note 1:
UARTEN
R/W-0 HC
R/W-0
WAKE
2:
(1)
Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
0 = Baud rate measurement disabled or completed
LPBACK
R/W-0
minimal
in hardware on following rising edge
before other data; cleared in hardware upon completion
U-0
—
port latches
UxMODE: UART
®
Encoder and Decoder Enable bit
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
x
MODE REGISTER
(1)
URXINV
IREN
R/W-0
R/W-0
Preliminary
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTSMD
(2)
BRGH
R/W-0
R/W-0
R/W-0
U-0
—
PDSEL<1:0>
© 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
UEN<1:0>
STSEL
R/W-0
R/W-0
bit 8
bit 0