MA240026 Microchip Technology, MA240026 Datasheet - Page 63

• Manufacturer Part Number: MA240026
• Description: Daughter Cards & OEM Boards PIC24FJ16MC102 Plug-In Module
• Manufacturer: Microchip Technology

Specifications of MA240026

• Rohs: yes
• Data Bus Width: 16 bit
• Description/function: PIC24F 28 Pin QFN to 100 Pin Plug-in-Module
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V

7.0
The Interrupt Controller reduces the numerous periph-
eral interrupt request signals to a single interrupt
request signal to the PIC24FJ16MC101/102 CPU. It
has the following features:
• Up to eight processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table (IVT) is shown in
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24-
bit-wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
© 2011 Microchip Technology Inc.
source
support
Note 1: This data sheet summarizes the features
2: It
3: Some registers and associated bits
INTERRUPT CONTROLLER
Interrupt Vector Table
of the PIC24FJ16MC101/102 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupts”
(DS39707)
Reference Manual”, which is available
from
(www.microchip.com).
specifications in
cal Characteristics”
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
is
important
the
in
Microchip
the
Section 26.0 “Electri-
to
of this data sheet,
“PIC24F
note
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Figure
that
Family
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the
7-1.
Preliminary
in
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupts at any
other vector address.
PIC24FJ16MC101/102 devices implement up to 26
unique interrupts and 4 nonmaskable traps. These are
summarized in
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a way to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24FJ16MC101/102 device clears its registers
in response to a Reset, forcing the PC to zero. The
microcontroller then begins program execution at
location 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
is
PIC24FJ16MC101/102
Reset Sequence
provided
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Table 7-1
by
and
the
Figure
Table
ALTIVT
7-1. Access to the
7-2.
DS39997B-page 63
control
bit