S-24CS16A0I-D8S1G Seiko Instruments, S-24CS16A0I-D8S1G Datasheet - Page 18

• Manufacturer Part Number: S-24CS16A0I-D8S1G
• Description: IC EEPROM 16KBIT 400KHZ 8DIP
• Manufacturer: Seiko Instruments

Specifications of S-24CS16A0I-D8S1G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP
• Organization: 2 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 1 us
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18
LINE
SDA
2-WIRE CMOS SERIAL E
S-24CS16A
ADDRESS
7. 3 Sequential Read
DEVICE
When the E
start condition both in current and random read operations, it responds with an acknowledge.
An 8-bit data is then sent from the E
incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in the E
incremented and makes it possible to read data in succession. This is called “Sequential Read”.
The master device outputs stop condition not an acknowledge, the reading of E
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first memory address.
W
R
D
R
E
A
1
/
C
A
K
2
D7
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a
DATA (n)
2
PROM
ADR INC
D0
A
C
K
2
PROM synchronous to the SCL clock and the address counter is automatically
D7
Figure 19 Sequential Read
Seiko Instruments Inc.
DATA (n+1)
ADR INC
D0
A
C
K
D7
DATA (n+2)
2
ADR INC
PROM is ended.
D0
C
A
K
D7
Master Device
NO ACK from
DATA (n+x)
Rev.5.2
ADR INC
D0
2
PROM
00
O
S
P
T