MT46H16M16LFBF-6 IT:A Micron Technology Inc, MT46H16M16LFBF-6 IT:A Datasheet - Page 66

• Manufacturer Part Number: MT46H16M16LFBF-6 IT:A
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M16LFBF-6 IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant
• Other names: Q3368612

Timing Diagrams
Figure 37:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
DQ8–DQ15 and UDQS, collectively
DQ0–DQ7 and LDQS, collectively
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
Data Output Timing –
Notes:
UDQS
LDQS
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
1
1
2
2
2
2
2
2
2
7
7
7
7
7
7
7
2
7
2
2
7
7
6
6
1. DQ transitioning after DQS transitions defines the
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3.
4.
5.
6. The data valid window is derived for each DQS transition and is defined as
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
T1
byte, and UDQS defines the upper byte.
t
DQS transition and ends with the last valid DQ transition.
t
t
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
QH is derived from
HP is the lesser of
t HP
5
t
DQSQ,
t HP
5
t DQSQ
t QH
t DQSQ
T2
4
t QH
t
Data valid
CL or
t
3
t
QH, and Data Valid Window (x16)
window
HP:
Data valid
4
T2
T2
T2
window
t HP
3
T2
T2
T2
5
t
t
QH =
CH clock transition collectively when a bank is active.
t DQSQ
T2n
t QH
66
t DQSQ
Data valid
t QH
4
t
window
HP -
3
t HP
T2n
T2n
Data valid
T2n
4
window
3
5
T2n
T2n
T2n
t
QHS.
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSQ
t QH
256Mb: x16, x32 Mobile DDR SDRAM
t DQSQ
t QH
4
t HP
Data valid
3
window
Data valid
5
4
window
T3
T3
T3
3
T3
T3
T3
T3n
t
DQSQ window. LDQS defines the lower
t DQSQ
t DQSQ
t HP
t QH
t QH
5
Data valid
4
4
window
Data valid
3
3
window
T3n
T3n
T4
T3n
T3n
T3n
T3n
©2005 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t
QH -
t
DQSQ.