MT48V8M16LFB4-8 IT:G Micron Technology Inc, MT48V8M16LFB4-8 IT:G Datasheet - Page 20
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MT48V8M16LFB4-8 IT:G
Manufacturer Part Number
MT48V8M16LFB4-8 IT:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48V8M16LFB4-8 IT:G
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 8:
Table 7:
Write Burst Mode
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
CAS Latency
CAS Latency
latency is programmed to 2 clocks, the DQ will start driving after T1, and the data will be
valid by T2, as shown in Figure 8. Table 7 indicates the operating frequencies at which
each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
COMMAND
COMMAND
COMMAND
When M9 = 0, BL programmed into M0–M2 applies to both READ and WRITE burst. If
M9 = 1, all WRITE bursts will only be single location access regardless of the BL setting in
the mode register. READ burst lengths are unaffected by the state of M9.
CLK
CLK
CLK
DQ
DQ
DQ
Speed
-75M
-10
-8
READ
READ
READ
T0
T0
T0
t
t AC
LZ
CL = 1
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
D
t OH
OUT
CL = 3
20
CL = 1
≤ 50
≤ 40
–
T2
NOP
T2
NOP
T2
t
t AC
LZ
Allowable Operating Frequency (MHz)
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
128Mb: x16, x32 Mobile SDRAM
OUT
DON’T CARE
UNDEFINED
CL = 2
≤ 100
≤ 100
≤ 83
T4
©2001 Micron Technology, Inc. All rights reserved.
Register Definition
CL = 3
≤ 133
≤ 125
≤ 100