IS61LPD51236A-200B3-TR ISSI, Integrated Silicon Solution Inc, IS61LPD51236A-200B3-TR Datasheet - Page 18

• Manufacturer Part Number: IS61LPD51236A-200B3-TR
• Description: IC SRAM 18MBIT 200MHZ 165FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPD51236A-200B3-TR

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
IEEE 1149.1 SERIal BOUNDaRY SCaN (JTaG)
The IS61LPD/VPD51236A and IS61LPD/VPD102418A
have a serial boundary scan Test Access Port (TAP) in the
PBGA package only. (The TQFP package not available.)
This port operates in accordance with IEEE Standard
1149.1-1900, but does not include all functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because they place added delay
in the critical speed path of the SRAM. The TAP control-
ler operates in a manner that does not conflict with the
performance of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC standard 2.5V I/O
logic levels.
DISaBlING THE JTaG FEaTURE
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to V
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TaP CONTROllER BlOCK DIaGRaM
18
TMS
TCK
TDI
Selection Circuitry
TAP CONTROLLER
dd
through a pull-up resistor.
31 30 29
0
2
x
Bypass Register
Instruction Register
Identification Register
Boundary Scan Register*
. . . . .
1
0
. . .
TEST aCCESS PORT (TaP) - TEST ClOCK
The test clock is only used with theTAP controller.All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
TEST MODE SElECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used.The pin
is internally pulled up, resulting in a logic HIGH level.
TEST DaTa-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any regis-
ter. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an applica-
tion. TDI is connected to the Most Significant Bit (MSB)
on any register.
Integrated Silicon Solution, Inc. — 1-800-379-4774
2
2
1
1
0
0
Selection Circuitry
TDO
07/08/08
Rev. C