IS61LPD51236A-200B3-TR ISSI, Integrated Silicon Solution Inc, IS61LPD51236A-200B3-TR Datasheet - Page 8

• Manufacturer Part Number: IS61LPD51236A-200B3-TR
• Description: IC SRAM 18MBIT 200MHZ 165FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPD51236A-200B3-TR

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TRUTH TaBlE
NOTE:
8
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
OPERaTION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
WRITE = H for all BWx, BWE, GW HIGH.
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
the input data hold time.
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
(1-8)
(3CE option)
aDDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
CE2
H
H
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADSP ADSC
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
X
L
L
L
ADV WRITE
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
OE
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
ClK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
07/08/08
DQ
Q
Q
Q
Q
Q
D
D
D
D
D
Rev. C
Q