PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 17

• Manufacturer Part Number: PSD4235G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1969

PSD4235G2
Table 2.
CNTL2
RESET
PA0-PA7
PB0-PB7
PC0-PC7
PD0
PD1
Pin name
40
39
51-58
61-68
41-48
79
80
Pin description (for the LQFP package) (continued)
Pin
I
I
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Slew
Rate
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
Type
READ or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN - Program Select Enable, active low in code fetch bus cycle (80C51XA
mode).
2. BHE - high-byte enable, 16-bit data bus.
3. UDS - active low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 - Byte enable input.
5. LSTRB - low Strobe input.
This pin is also connected to the PLDs.
Active low input. Resets I/O Ports, PLD macrocells and some of the Configuration
registers and JTAG registers. Must be low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. CPLD macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. CPLD macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input - latches address on ADIO0-ADIO15.
2. AS input - latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O - standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O - standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN - clock input to the CPLD macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
Description
Pin description
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